Lines Matching +full:switch +full:- +full:frequency +full:- +full:hz

1 // SPDX-License-Identifier: GPL-2.0-only
8  * enough to be briefly explained. It consists of one 8-bit counter. The PWM
11  * to reset it. This implies that the higher the frequency the less remaining
15  * +-----------+--------+--------------+-----------+---------------+
16  * | prescaler |  reset | counter bits | frequency | period length |
17  * +-----------+--------+--------------+-----------+---------------+
18  * |         0 | cnt[7] |     cnt[6:0] |    250 Hz |    4000000 ns |
19  * |         1 | cnt[6] |     cnt[5:0] |    500 Hz |    2000000 ns |
22  * +-----------+--------+--------------+-----------+---------------+
25  * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26  * - The hardware cannot atomically set the prescaler and the counter value,
28  * - The counter is not reset if you switch the prescaler which leads
30  * - The duty cycle will switch immediately and not after a complete cycle.
31  * - Depending on the actual implementation, disabling the PWM might have
33  *   it will automatically switch back to GPIO mode.
55 #define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)	(1 << (7 - (prescaler)))
64  *   max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC
65  *   max_duty_cycle = 1 << (7 - prescaler)
79 	regmap_read((priv)->regmap, (priv)->offset + (reg), (val))
81 	regmap_write((priv)->regmap, (priv)->offset + (reg), (val))
103 	state->enabled = reg & SL28CPLD_PWM_CTRL_ENABLE;  in sl28cpld_pwm_get_state()
106 	state->period = SL28CPLD_PWM_PERIOD(prescaler);  in sl28cpld_pwm_get_state()
109 	state->duty_cycle = SL28CPLD_PWM_TO_DUTY_CYCLE(reg);  in sl28cpld_pwm_get_state()
110 	state->polarity = PWM_POLARITY_NORMAL;  in sl28cpld_pwm_get_state()
120 	state->duty_cycle = min(state->duty_cycle, state->period);  in sl28cpld_pwm_get_state()
135 	if (state->polarity != PWM_POLARITY_NORMAL)  in sl28cpld_pwm_apply()
136 		return -EINVAL;  in sl28cpld_pwm_apply()
142 	prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period);  in sl28cpld_pwm_apply()
146 		return -ERANGE;  in sl28cpld_pwm_apply()
149 	if (state->enabled)  in sl28cpld_pwm_apply()
152 	cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle);  in sl28cpld_pwm_apply()
158 	 * care about the frequency because its "all-one" in either case.  in sl28cpld_pwm_apply()
170 	 * To avoid glitches when we switch the prescaler, we have to make sure  in sl28cpld_pwm_apply()
178 	write_duty_cycle_first = pwm->state.period > state->period;  in sl28cpld_pwm_apply()
210 	if (!pdev->dev.parent) {  in sl28cpld_pwm_probe()
211 		dev_err(&pdev->dev, "no parent device\n");  in sl28cpld_pwm_probe()
212 		return -ENODEV;  in sl28cpld_pwm_probe()
215 	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*priv));  in sl28cpld_pwm_probe()
220 	priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);  in sl28cpld_pwm_probe()
221 	if (!priv->regmap) {  in sl28cpld_pwm_probe()
222 		dev_err(&pdev->dev, "could not get parent regmap\n");  in sl28cpld_pwm_probe()
223 		return -ENODEV;  in sl28cpld_pwm_probe()
226 	ret = device_property_read_u32(&pdev->dev, "reg", &priv->offset);  in sl28cpld_pwm_probe()
228 		dev_err(&pdev->dev, "no 'reg' property found (%pe)\n",  in sl28cpld_pwm_probe()
230 		return -EINVAL;  in sl28cpld_pwm_probe()
234 	chip->ops = &sl28cpld_pwm_ops;  in sl28cpld_pwm_probe()
236 	ret = devm_pwmchip_add(&pdev->dev, chip);  in sl28cpld_pwm_probe()
238 		dev_err(&pdev->dev, "failed to add PWM chip (%pe)",  in sl28cpld_pwm_probe()
247 	{ .compatible = "kontron,sl28cpld-pwm" },
255 		.name = "sl28cpld-pwm",