1 // SPDX-License-Identifier: GPL-2.0-only
8  * enough to be briefly explained. It consists of one 8-bit counter. The PWM
14  * Let cnt[7:0] be the counter, clocked at 32kHz:
15  * +-----------+--------+--------------+-----------+---------------+
17  * +-----------+--------+--------------+-----------+---------------+
18  * |         0 | cnt[7] |     cnt[6:0] |    250 Hz |    4000000 ns |
19  * |         1 | cnt[6] |     cnt[5:0] |    500 Hz |    2000000 ns |
20  * |         2 | cnt[5] |     cnt[4:0] |     1 kHz |    1000000 ns |
21  * |         3 | cnt[4] |     cnt[3:0] |     2 kHz |     500000 ns |
22  * +-----------+--------+--------------+-----------+---------------+
25  * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26  * - The hardware cannot atomically set the prescaler and the counter value,
28  * - The counter is not reset if you switch the prescaler which leads
30  * - The duty cycle will switch immediately and not after a complete cycle.
31  * - Depending on the actual implementation, disabling the PWM might have
48 #define SL28CPLD_PWM_CTRL			0x00
50 #define   SL28CPLD_PWM_CTRL_PRESCALER_MASK	GENMASK(1, 0)
51 #define SL28CPLD_PWM_CYCLE			0x01
52 #define   SL28CPLD_PWM_CYCLE_MAX		GENMASK(6, 0)
55 #define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)	(1 << (7 - (prescaler)))
60  * We calculate the duty cycle like this:
64  *   max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC
65  *   max_duty_cycle = 1 << (7 - prescaler)
79 	regmap_read((priv)->regmap, (priv)->offset + (reg), (val))
81 	regmap_write((priv)->regmap, (priv)->offset + (reg), (val))
103 	state->enabled = reg & SL28CPLD_PWM_CTRL_ENABLE;  in sl28cpld_pwm_get_state()
106 	state->period = SL28CPLD_PWM_PERIOD(prescaler);  in sl28cpld_pwm_get_state()
109 	state->duty_cycle = SL28CPLD_PWM_TO_DUTY_CYCLE(reg);  in sl28cpld_pwm_get_state()
110 	state->polarity = PWM_POLARITY_NORMAL;  in sl28cpld_pwm_get_state()
120 	state->duty_cycle = min(state->duty_cycle, state->period);  in sl28cpld_pwm_get_state()
122 	return 0;  in sl28cpld_pwm_get_state()
129 	unsigned int cycle, prescaler;  in sl28cpld_pwm_apply()  local
135 	if (state->polarity != PWM_POLARITY_NORMAL)  in sl28cpld_pwm_apply()
136 		return -EINVAL;  in sl28cpld_pwm_apply()
142 	prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period);  in sl28cpld_pwm_apply()
146 		return -ERANGE;  in sl28cpld_pwm_apply()
149 	if (state->enabled)  in sl28cpld_pwm_apply()
152 	cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle);  in sl28cpld_pwm_apply()
153 	cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler));  in sl28cpld_pwm_apply()
157 	 * cycle if the prescaler is 0. Set prescaler to 1 instead. We don't  in sl28cpld_pwm_apply()
158 	 * care about the frequency because its "all-one" in either case.  in sl28cpld_pwm_apply()
161 	 * if the prescaler is 0 we can have this particular value.  in sl28cpld_pwm_apply()
163 	if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) {  in sl28cpld_pwm_apply()
166 		cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1);  in sl28cpld_pwm_apply()
171 	 * we have a valid duty cycle for the new mode.  in sl28cpld_pwm_apply()
174 	 * account to decide whether we have to write the duty cycle or the new  in sl28cpld_pwm_apply()
176 	 * write the duty cycle first.  in sl28cpld_pwm_apply()
178 	write_duty_cycle_first = pwm->state.period > state->period;  in sl28cpld_pwm_apply()
181 		ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);  in sl28cpld_pwm_apply()
191 		ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);  in sl28cpld_pwm_apply()
196 	return 0;  in sl28cpld_pwm_apply()
210 	if (!pdev->dev.parent) {  in sl28cpld_pwm_probe()
211 		dev_err(&pdev->dev, "no parent device\n");  in sl28cpld_pwm_probe()
212 		return -ENODEV;  in sl28cpld_pwm_probe()
215 	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*priv));  in sl28cpld_pwm_probe()
220 	priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);  in sl28cpld_pwm_probe()
221 	if (!priv->regmap) {  in sl28cpld_pwm_probe()
222 		dev_err(&pdev->dev, "could not get parent regmap\n");  in sl28cpld_pwm_probe()
223 		return -ENODEV;  in sl28cpld_pwm_probe()
226 	ret = device_property_read_u32(&pdev->dev, "reg", &priv->offset);  in sl28cpld_pwm_probe()
228 		dev_err(&pdev->dev, "no 'reg' property found (%pe)\n",  in sl28cpld_pwm_probe()
230 		return -EINVAL;  in sl28cpld_pwm_probe()
234 	chip->ops = &sl28cpld_pwm_ops;  in sl28cpld_pwm_probe()
236 	ret = devm_pwmchip_add(&pdev->dev, chip);  in sl28cpld_pwm_probe()
238 		dev_err(&pdev->dev, "failed to add PWM chip (%pe)",  in sl28cpld_pwm_probe()
243 	return 0;  in sl28cpld_pwm_probe()
247 	{ .compatible = "kontron,sl28cpld-pwm" },
255 		.name = "sl28cpld-pwm",