Lines Matching full:period
73 u32 clk_div, period, high_width, value; in mtk_disp_pwm_apply() local
108 * Find period, high_width and clk_div to suit duty_ns and period_ns. in mtk_disp_pwm_apply()
109 * Calculate proper div value to keep period value in the bound. in mtk_disp_pwm_apply()
111 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE in mtk_disp_pwm_apply()
114 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1 in mtk_disp_pwm_apply()
118 clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >> in mtk_disp_pwm_apply()
129 period = mul_u64_u64_div_u64(state->period, rate, div); in mtk_disp_pwm_apply()
130 if (period > 0) in mtk_disp_pwm_apply()
131 period--; in mtk_disp_pwm_apply()
134 value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); in mtk_disp_pwm_apply()
177 u64 rate, period, high_width; in mtk_disp_pwm_get_state() local
210 period = FIELD_GET(PWM_PERIOD_MASK, con1); in mtk_disp_pwm_get_state()
212 * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30, in mtk_disp_pwm_get_state()
213 * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow. in mtk_disp_pwm_get_state()
215 state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate); in mtk_disp_pwm_get_state()