Lines Matching full:period
17 * As setting the period/duty cycle takes 4 register writes, there is a window
18 * in which this races against the start of a new period.
23 * period. Therefore to get a 0% waveform, the output is set the max high/low
25 * If the duty cycle is 0%, and the requested period is less than the
26 * available period resolution, this will manifest as a ~100% waveform (with
28 * - The PWM period is set for the whole IP block not per channel. The driver
29 * will only change the period if no other PWM output is enabled.
59 struct mutex lock; /* protects the shared period */
71 bool enable, u64 period)
94 * applied to the waveform at the beginning of the next period.
98 mchp_core_pwm->update_timestamp = ktime_add_ns(ktime_get(), period);
109 * once the current period has ended.
139 * Calculate the duty cycle in multiples of the prescaled period:
190 * Calculate the period cycles and prescale values.
191 * The registers are each 8 bits wide & multiplied to compute the period
194 * period = -------------------------------------
196 * so the maximum period that can be generated is 0x10000 times the
197 * period of the input clock.
201 * of the clock period attainable is (0xff + 1) * (0xfe + 1) = 0xff00
206 * It's therefore not possible to set a period lower than 1/clk_rate, so
207 * if tmp is 0, abort. Without aborting, we will set a period that is
211 tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC);
223 * is as finegrain as possible, while also keeping the period less than
230 * Integer division will ensure a round down, so the period will thereby
237 * As we must produce a period less than that requested, and for the
248 * period * clk_rate
253 * period * clk_rate
261 * period * clk_rate
284 mchp_core_pwm_enable(chip, pwm, false, pwm->state.period);
305 * As all the channels share the same period, do not allow it to be
307 * If the period is locked, it may not be possible to use a period
328 * The period is locked and we cannot change this, so we abort.
340 * Because the period is not per channel, it is possible that the
341 * requested duty cycle is longer than the period, in which case cap it
342 * to the period, IOW a 100% duty cycle.
354 mchp_core_pwm_enable(chip, pwm, true, pwm->state.period);
396 * Calculating the period:
397 * The registers are each 8 bits wide & multiplied to compute the period
400 * period = -------------------------------------
411 state->period = (period_steps + 1) * (prescale + 1);
412 state->period *= NSEC_PER_SEC;
413 state->period = DIV64_U64_ROUND_UP(state->period, rate);
421 state->duty_cycle = state->period;
422 state->period *= 2;