Lines Matching +full:duty +full:- +full:cycle
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved.
8 * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
11 * - If the IP block is configured without "shadow registers", all register
17 * As setting the period/duty cycle takes 4 register writes, there is a window
19 * - The IP block has no concept of a duty cycle, only rising/falling edges of
25 * If the duty cycle is 0%, and the requested period is less than the
28 * - The PWM period is set for the whole IP block not per channel. The driver
78 * 0-7 and the upper reg 8-15. Check if the pwm is in the upper reg
81 reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3);
82 shift = pwm->hwpwm & 7;
84 channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);
88 writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
89 mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);
90 mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;
95 * This is a NO-OP if the channel does not have shadow registers.
97 if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm))
98 mchp_core_pwm->update_timestamp = ktime_add_ns(ktime_get(), period);
112 if (mchp_core_pwm->sync_update_mask & (1 << channel)) {
117 remaining_ns = ktime_to_ns(ktime_sub(mchp_core_pwm->update_timestamp,
139 * Calculate the duty cycle in multiples of the prescaled period:
145 duty_steps = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, tmp);
167 if (state->polarity == PWM_POLARITY_INVERSED) {
180 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
181 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
194 * period = -------------------------------------
199 * attain a 100% duty cycle if the full range of period_steps is used.
209 * neg-/pos-edge issue described in the limitations.
211 tmp = mul_u64_u64_div_u64(state->period, clk_rate, NSEC_PER_SEC);
222 * Here the idea is to pick values so that the selection of duty cycles
242 return -EINVAL;
249 * prescale = ------------------------- - 1
254 * ------------------- was precomputed as `tmp`
257 *prescale = ((u16)tmp) / (MCHPCOREPWM_PERIOD_STEPS_MAX + 1) - 1;
262 * period_steps = ----------------------------- - 1
283 if (!state->enabled) {
284 mchp_core_pwm_enable(chip, pwm, false, pwm->state.period);
293 clk_rate = clk_get_rate(mchp_core_pwm->clk);
295 return -EINVAL;
302 * If the only thing that has changed is the duty cycle or the polarity,
303 * we can shortcut the calculations and just compute/apply the new duty
304 * cycle pos & neg edges
310 period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);
316 hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
317 hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
321 return -EINVAL;
326 * or 0% relative duty cycle, as explained above in
331 return -EINVAL;
341 * requested duty cycle is longer than the period, in which case cap it
342 * to the period, IOW a 100% duty cycle.
348 writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
349 writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
354 mchp_core_pwm_enable(chip, pwm, true, pwm->state.period);
365 mutex_lock(&mchp_core_pwm->lock);
367 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);
371 mutex_unlock(&mchp_core_pwm->lock);
384 mutex_lock(&mchp_core_pwm->lock);
386 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);
388 if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm))
389 state->enabled = true;
391 state->enabled = false;
393 rate = clk_get_rate(mchp_core_pwm->clk);
400 * period = -------------------------------------
408 prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
409 period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
411 state->period = (period_steps + 1) * (prescale + 1);
412 state->period *= NSEC_PER_SEC;
413 state->period = DIV64_U64_ROUND_UP(state->period, rate);
415 posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
416 negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
418 mutex_unlock(&mchp_core_pwm->lock);
421 state->duty_cycle = state->period;
422 state->period *= 2;
424 duty_steps = abs((s16)posedge - (s16)negedge);
425 state->duty_cycle = duty_steps * (prescale + 1) * NSEC_PER_SEC;
426 state->duty_cycle = DIV64_U64_ROUND_UP(state->duty_cycle, rate);
429 state->polarity = negedge < posedge ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
441 .compatible = "microchip,corepwm-rtl-v4",
454 chip = devm_pwmchip_alloc(&pdev->dev, 16, sizeof(*mchp_core_pwm));
459 mchp_core_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
460 if (IS_ERR(mchp_core_pwm->base))
461 return PTR_ERR(mchp_core_pwm->base);
463 mchp_core_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL);
464 if (IS_ERR(mchp_core_pwm->clk))
465 return dev_err_probe(&pdev->dev, PTR_ERR(mchp_core_pwm->clk),
468 if (of_property_read_u32(pdev->dev.of_node, "microchip,sync-update-mask",
469 &mchp_core_pwm->sync_update_mask))
470 mchp_core_pwm->sync_update_mask = 0;
472 mutex_init(&mchp_core_pwm->lock);
474 chip->ops = &mchp_core_pwm_ops;
476 mchp_core_pwm->channel_enabled = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0));
477 mchp_core_pwm->channel_enabled |=
478 readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(1)) << 8;
484 writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);
485 mchp_core_pwm->update_timestamp = ktime_get();
487 ret = devm_pwmchip_add(&pdev->dev, chip);
489 return dev_err_probe(&pdev->dev, ret, "Failed to add pwmchip\n");
496 .name = "mchp-core-pwm",