Lines Matching defs:mchp_core_pwm
73 struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
84 channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);
88 writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
89 mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm);
90 mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm;
97 if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm))
98 mchp_core_pwm->update_timestamp = ktime_add_ns(ktime_get(), period);
101 static void mchp_core_pwm_wait_for_sync_update(struct mchp_core_pwm_chip *mchp_core_pwm,
112 if (mchp_core_pwm->sync_update_mask & (1 << channel)) {
117 remaining_ns = ktime_to_ns(ktime_sub(mchp_core_pwm->update_timestamp,
154 struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
180 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
181 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
276 struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
293 clk_rate = clk_get_rate(mchp_core_pwm->clk);
310 period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm);
316 hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
317 hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
348 writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
349 writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
362 struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
365 mutex_lock(&mchp_core_pwm->lock);
367 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);
371 mutex_unlock(&mchp_core_pwm->lock);
379 struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip);
384 mutex_lock(&mchp_core_pwm->lock);
386 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm);
388 if (mchp_core_pwm->channel_enabled & (1 << pwm->hwpwm))
393 rate = clk_get_rate(mchp_core_pwm->clk);
408 prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
409 period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
415 posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
416 negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
418 mutex_unlock(&mchp_core_pwm->lock);
450 struct mchp_core_pwm_chip *mchp_core_pwm;
454 chip = devm_pwmchip_alloc(&pdev->dev, 16, sizeof(*mchp_core_pwm));
457 mchp_core_pwm = to_mchp_core_pwm(chip);
459 mchp_core_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
460 if (IS_ERR(mchp_core_pwm->base))
461 return PTR_ERR(mchp_core_pwm->base);
463 mchp_core_pwm->clk = devm_clk_get_enabled(&pdev->dev, NULL);
464 if (IS_ERR(mchp_core_pwm->clk))
465 return dev_err_probe(&pdev->dev, PTR_ERR(mchp_core_pwm->clk),
469 &mchp_core_pwm->sync_update_mask))
470 mchp_core_pwm->sync_update_mask = 0;
472 mutex_init(&mchp_core_pwm->lock);
476 mchp_core_pwm->channel_enabled = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0));
477 mchp_core_pwm->channel_enabled |=
478 readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(1)) << 8;
484 writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);
485 mchp_core_pwm->update_timestamp = ktime_get();