1 // SPDX-License-Identifier: GPL-2.0-only
24  *    a subsequent rising edge of the trigger bit.
26  * 3) If the smooth bit and trigger bit are both low, the output is a constant
29  * 4) If the smooth bit is set on the rising edge of the trigger bit, output
69  * Clear trigger bit but set smooth bit to maintain old output.
74 	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);  in kona_pwmc_prepare_for_settings()  local
76 	value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);  in kona_pwmc_prepare_for_settings()
77 	value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));  in kona_pwmc_prepare_for_settings()
78 	writel(value, kp->base + PWM_CONTROL_OFFSET);  in kona_pwmc_prepare_for_settings()
81 	 * There must be a min 400ns delay between clearing trigger and setting  in kona_pwmc_prepare_for_settings()
89 	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);  in kona_pwmc_apply_settings()  local
91 	/* Set trigger bit and clear smooth bit to apply new settings */  in kona_pwmc_apply_settings()
92 	value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));  in kona_pwmc_apply_settings()
93 	value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);  in kona_pwmc_apply_settings()
94 	writel(value, kp->base + PWM_CONTROL_OFFSET);  in kona_pwmc_apply_settings()
96 	/* Trigger bit must be held high for at least 400 ns. */  in kona_pwmc_apply_settings()
106 	unsigned int value, chan = pwm->hwpwm;  in kona_pwmc_config()  local
119 	rate = clk_get_rate(kp->clk);  in kona_pwmc_config()
129 			return -EINVAL;  in kona_pwmc_config()
137 			return -EINVAL;  in kona_pwmc_config()
142 	value = readl(kp->base + PRESCALE_OFFSET);  in kona_pwmc_config()
143 	value &= ~PRESCALE_MASK(chan);  in kona_pwmc_config()
144 	value |= prescale << PRESCALE_SHIFT(chan);  in kona_pwmc_config()
145 	writel(value, kp->base + PRESCALE_OFFSET);  in kona_pwmc_config()
147 	writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));  in kona_pwmc_config()
149 	writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));  in kona_pwmc_config()
160 	unsigned int chan = pwm->hwpwm;  in kona_pwmc_set_polarity()
161 	unsigned int value;  in kona_pwmc_set_polarity()  local
164 	ret = clk_prepare_enable(kp->clk);  in kona_pwmc_set_polarity()
172 	value = readl(kp->base + PWM_CONTROL_OFFSET);  in kona_pwmc_set_polarity()
175 		value |= 1 << PWM_CONTROL_POLARITY_SHIFT(chan);  in kona_pwmc_set_polarity()
177 		value &= ~(1 << PWM_CONTROL_POLARITY_SHIFT(chan));  in kona_pwmc_set_polarity()
179 	writel(value, kp->base + PWM_CONTROL_OFFSET);  in kona_pwmc_set_polarity()
183 	clk_disable_unprepare(kp->clk);  in kona_pwmc_set_polarity()
193 	ret = clk_prepare_enable(kp->clk);  in kona_pwmc_enable()
205 	unsigned int chan = pwm->hwpwm;  in kona_pwmc_disable()
206 	unsigned int value;  in kona_pwmc_disable()  local
211 	writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));  in kona_pwmc_disable()
212 	writel(0, kp->base + PERIOD_COUNT_OFFSET(chan));  in kona_pwmc_disable()
215 	value = readl(kp->base + PRESCALE_OFFSET);  in kona_pwmc_disable()
216 	value &= ~PRESCALE_MASK(chan);  in kona_pwmc_disable()
217 	writel(value, kp->base + PRESCALE_OFFSET);  in kona_pwmc_disable()
221 	clk_disable_unprepare(kp->clk);  in kona_pwmc_disable()
229 	bool enabled = pwm->state.enabled;  in kona_pwmc_apply()
231 	if (state->polarity != pwm->state.polarity) {  in kona_pwmc_apply()
237 		err = kona_pwmc_set_polarity(chip, pwm, state->polarity);  in kona_pwmc_apply()
241 		pwm->state.polarity = state->polarity;  in kona_pwmc_apply()
244 	if (!state->enabled) {  in kona_pwmc_apply()
262 	err = kona_pwmc_config(chip, pwm, state->duty_cycle, state->period);  in kona_pwmc_apply()
263 	if (err && !pwm->state.enabled)  in kona_pwmc_apply()
264 		clk_disable_unprepare(kp->clk);  in kona_pwmc_apply()
278 	unsigned int value = 0;  in kona_pwmc_probe()  local
281 	chip = devm_pwmchip_alloc(&pdev->dev, 6, sizeof(*kp));  in kona_pwmc_probe()
286 	chip->ops = &kona_pwm_ops;  in kona_pwmc_probe()
288 	kp->base = devm_platform_ioremap_resource(pdev, 0);  in kona_pwmc_probe()
289 	if (IS_ERR(kp->base))  in kona_pwmc_probe()
290 		return PTR_ERR(kp->base);  in kona_pwmc_probe()
292 	kp->clk = devm_clk_get(&pdev->dev, NULL);  in kona_pwmc_probe()
293 	if (IS_ERR(kp->clk)) {  in kona_pwmc_probe()
294 		dev_err(&pdev->dev, "failed to get clock: %ld\n",  in kona_pwmc_probe()
295 			PTR_ERR(kp->clk));  in kona_pwmc_probe()
296 		return PTR_ERR(kp->clk);  in kona_pwmc_probe()
299 	ret = clk_prepare_enable(kp->clk);  in kona_pwmc_probe()
301 		dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);  in kona_pwmc_probe()
306 	for (chan = 0; chan < chip->npwm; chan++)  in kona_pwmc_probe()
307 		value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));  in kona_pwmc_probe()
309 	writel(value, kp->base + PWM_CONTROL_OFFSET);  in kona_pwmc_probe()
311 	clk_disable_unprepare(kp->clk);  in kona_pwmc_probe()
313 	ret = devm_pwmchip_add(&pdev->dev, chip);  in kona_pwmc_probe()
315 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);  in kona_pwmc_probe()
321 	{ .compatible = "brcm,kona-pwm" },
328 		.name = "bcm-kona-pwm",
335 MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");