1 // SPDX-License-Identifier: GPL-2.0-only
8  * Links to reference manuals for the supported PWM chips can be found in
12  * - Periods start with the inactive level.
13  * - Hardware has to be stopped in general to update settings.
16  * - When atmel_pwm_apply() is called with state->enabled=false a change in
17  *   state->polarity isn't honored.
18  * - Instead of sleeping to wait for a completed period, the interrupt
104 	return readl_relaxed(chip->base + offset);  in atmel_pwm_readl()
110 	writel_relaxed(val, chip->base + offset);  in atmel_pwm_writel()
140 	chip->update_pending &= ~isr;  in atmel_pwm_update_pending()
151 	chip->update_pending |= (1 << ch);  in atmel_pwm_set_pending()
158 	if (chip->update_pending & (1 << ch)) {  in atmel_pwm_test_pending()
161 		if (chip->update_pending & (1 << ch))  in atmel_pwm_test_pending()
177 	return ret ? -ETIMEDOUT : 0;  in atmel_pwm_wait_nonpending()
186 	unsigned long long cycles = state->period;  in atmel_pwm_calculate_cprd_and_pres()
198 	shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;  in atmel_pwm_calculate_cprd_and_pres()
202 		return -EINVAL;  in atmel_pwm_calculate_cprd_and_pres()
219 	unsigned long long cycles = state->duty_cycle;  in atmel_pwm_calculate_cdty()
224 	*cdty = cprd - cycles;  in atmel_pwm_calculate_cdty()
233 	if (atmel_pwm->data->regs.duty_upd ==  in atmel_pwm_update_cdty()
234 	    atmel_pwm->data->regs.period_upd) {  in atmel_pwm_update_cdty()
235 		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);  in atmel_pwm_update_cdty()
237 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);  in atmel_pwm_update_cdty()
240 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,  in atmel_pwm_update_cdty()
241 			    atmel_pwm->data->regs.duty_upd, cdty);  in atmel_pwm_update_cdty()
242 	atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);  in atmel_pwm_update_cdty()
251 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,  in atmel_pwm_set_cprd_cdty()
252 			    atmel_pwm->data->regs.duty, cdty);  in atmel_pwm_set_cprd_cdty()
253 	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,  in atmel_pwm_set_cprd_cdty()
254 			    atmel_pwm->data->regs.period, cprd);  in atmel_pwm_set_cprd_cdty()
263 	atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);  in atmel_pwm_disable()
265 	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);  in atmel_pwm_disable()
273 	while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&  in atmel_pwm_disable()
278 		clk_disable(atmel_pwm->clk);  in atmel_pwm_disable()
289 	if (state->enabled) {  in atmel_pwm_apply()
290 		unsigned long clkrate = clk_get_rate(atmel_pwm->clk);  in atmel_pwm_apply()
292 		if (pwm->state.enabled &&  in atmel_pwm_apply()
293 		    pwm->state.polarity == state->polarity &&  in atmel_pwm_apply()
294 		    pwm->state.period == state->period) {  in atmel_pwm_apply()
295 			u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);  in atmel_pwm_apply()
297 			cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,  in atmel_pwm_apply()
298 						  atmel_pwm->data->regs.period);  in atmel_pwm_apply()
316 		if (pwm->state.enabled) {  in atmel_pwm_apply()
319 			ret = clk_enable(atmel_pwm->clk);  in atmel_pwm_apply()
327 		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);  in atmel_pwm_apply()
329 		if (state->polarity == PWM_POLARITY_NORMAL)  in atmel_pwm_apply()
333 		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);  in atmel_pwm_apply()
335 		atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);  in atmel_pwm_apply()
336 	} else if (pwm->state.enabled) {  in atmel_pwm_apply()
350 	cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);  in atmel_pwm_get_state()
352 	if (sr & (1 << pwm->hwpwm)) {  in atmel_pwm_get_state()
353 		unsigned long rate = clk_get_rate(atmel_pwm->clk);  in atmel_pwm_get_state()
359 		cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,  in atmel_pwm_get_state()
360 					  atmel_pwm->data->regs.period);  in atmel_pwm_get_state()
363 		state->period = DIV64_U64_ROUND_UP(tmp, rate);  in atmel_pwm_get_state()
366 		atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);  in atmel_pwm_get_state()
368 		cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,  in atmel_pwm_get_state()
369 					  atmel_pwm->data->regs.duty);  in atmel_pwm_get_state()
370 		tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;  in atmel_pwm_get_state()
372 		state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);  in atmel_pwm_get_state()
374 		state->enabled = true;  in atmel_pwm_get_state()
376 		state->enabled = false;  in atmel_pwm_get_state()
380 		state->polarity = PWM_POLARITY_INVERSED;  in atmel_pwm_get_state()
382 		state->polarity = PWM_POLARITY_NORMAL;  in atmel_pwm_get_state()
433 		.compatible = "atmel,at91sam9rl-pwm",
436 		.compatible = "atmel,sama5d3-pwm",
439 		.compatible = "atmel,sama5d2-pwm",
442 		.compatible = "microchip,sam9x60-pwm",
461 	cnt = bitmap_weight(&sr, chip->npwm);  in atmel_pwm_enable_clk_if_on()
467 		ret = clk_enable(atmel_pwm->clk);  in atmel_pwm_enable_clk_if_on()
481 	while (cnt--)  in atmel_pwm_enable_clk_if_on()
482 		clk_disable(atmel_pwm->clk);  in atmel_pwm_enable_clk_if_on()
493 	chip = devm_pwmchip_alloc(&pdev->dev, 4, sizeof(*atmel_pwm));  in atmel_pwm_probe()
498 	atmel_pwm->data = of_device_get_match_data(&pdev->dev);  in atmel_pwm_probe()
500 	atmel_pwm->update_pending = 0;  in atmel_pwm_probe()
502 	atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);  in atmel_pwm_probe()
503 	if (IS_ERR(atmel_pwm->base))  in atmel_pwm_probe()
504 		return PTR_ERR(atmel_pwm->base);  in atmel_pwm_probe()
506 	atmel_pwm->clk = devm_clk_get_prepared(&pdev->dev, NULL);  in atmel_pwm_probe()
507 	if (IS_ERR(atmel_pwm->clk))  in atmel_pwm_probe()
508 		return dev_err_probe(&pdev->dev, PTR_ERR(atmel_pwm->clk),  in atmel_pwm_probe()
511 	chip->ops = &atmel_pwm_ops;  in atmel_pwm_probe()
517 	ret = devm_pwmchip_add(&pdev->dev, chip);  in atmel_pwm_probe()
519 		dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");  in atmel_pwm_probe()
533 		.name = "atmel-pwm",
540 MODULE_ALIAS("platform:atmel-pwm");