Lines Matching +full:pwm +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
8 * Links to reference manuals for the supported PWM chips can be found in
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
29 #include <linux/pwm.h>
32 /* The following is global registers for PWM controller */
40 /* The following register is PWM channel related registers */
50 /* The following registers for PWM v1 */
55 /* The following registers for PWM v2 */
87 * pending we delay disabling the PWM until the new configuration is
105 unsigned long offset) in atmel_pwm_readl() argument
107 return readl_relaxed(chip->base + offset); in atmel_pwm_readl()
111 unsigned long offset, unsigned long val) in atmel_pwm_writel() argument
113 writel_relaxed(val, chip->base + offset); in atmel_pwm_writel()
117 unsigned int ch, unsigned long offset) in atmel_pwm_ch_readl() argument
121 return atmel_pwm_readl(chip, base + offset); in atmel_pwm_ch_readl()
125 unsigned int ch, unsigned long offset, in atmel_pwm_ch_writel() argument
130 atmel_pwm_writel(chip, base + offset, val); in atmel_pwm_ch_writel()
143 chip->update_pending &= ~isr; in atmel_pwm_update_pending()
148 spin_lock(&chip->lock); in atmel_pwm_set_pending()
156 chip->update_pending |= (1 << ch); in atmel_pwm_set_pending()
158 spin_unlock(&chip->lock); in atmel_pwm_set_pending()
165 spin_lock(&chip->lock); in atmel_pwm_test_pending()
167 if (chip->update_pending & (1 << ch)) { in atmel_pwm_test_pending()
170 if (chip->update_pending & (1 << ch)) in atmel_pwm_test_pending()
174 spin_unlock(&chip->lock); in atmel_pwm_test_pending()
188 return ret ? -ETIMEDOUT : 0; in atmel_pwm_wait_nonpending()
197 unsigned long long cycles = state->period; in atmel_pwm_calculate_cprd_and_pres()
209 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits; in atmel_pwm_calculate_cprd_and_pres()
213 return -EINVAL; in atmel_pwm_calculate_cprd_and_pres()
230 unsigned long long cycles = state->duty_cycle; in atmel_pwm_calculate_cdty()
235 *cdty = cprd - cycles; in atmel_pwm_calculate_cdty()
238 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_update_cdty() argument
244 if (atmel_pwm->data->regs.duty_upd == in atmel_pwm_update_cdty()
245 atmel_pwm->data->regs.period_upd) { in atmel_pwm_update_cdty()
246 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_update_cdty()
248 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_update_cdty()
251 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_update_cdty()
252 atmel_pwm->data->regs.duty_upd, cdty); in atmel_pwm_update_cdty()
253 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm); in atmel_pwm_update_cdty()
257 struct pwm_device *pwm, in atmel_pwm_set_cprd_cdty() argument
262 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
263 atmel_pwm->data->regs.duty, cdty); in atmel_pwm_set_cprd_cdty()
264 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
265 atmel_pwm->data->regs.period, cprd); in atmel_pwm_set_cprd_cdty()
268 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_disable() argument
274 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm); in atmel_pwm_disable()
276 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); in atmel_pwm_disable()
279 * Wait for the PWM channel disable operation to be effective before in atmel_pwm_disable()
284 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && in atmel_pwm_disable()
289 clk_disable(atmel_pwm->clk); in atmel_pwm_disable()
292 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_apply() argument
300 if (state->enabled) { in atmel_pwm_apply()
301 unsigned long clkrate = clk_get_rate(atmel_pwm->clk); in atmel_pwm_apply()
303 if (pwm->state.enabled && in atmel_pwm_apply()
304 pwm->state.polarity == state->polarity && in atmel_pwm_apply()
305 pwm->state.period == state->period) { in atmel_pwm_apply()
306 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_apply()
308 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, in atmel_pwm_apply()
309 atmel_pwm->data->regs.period); in atmel_pwm_apply()
313 atmel_pwm_update_cdty(chip, pwm, cdty); in atmel_pwm_apply()
327 if (pwm->state.enabled) { in atmel_pwm_apply()
328 atmel_pwm_disable(chip, pwm, false); in atmel_pwm_apply()
330 ret = clk_enable(atmel_pwm->clk); in atmel_pwm_apply()
338 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_apply()
340 if (state->polarity == PWM_POLARITY_NORMAL) in atmel_pwm_apply()
344 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_apply()
345 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty); in atmel_pwm_apply()
346 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm); in atmel_pwm_apply()
347 } else if (pwm->state.enabled) { in atmel_pwm_apply()
348 atmel_pwm_disable(chip, pwm, true); in atmel_pwm_apply()
354 static int atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_get_state() argument
361 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_get_state()
363 if (sr & (1 << pwm->hwpwm)) { in atmel_pwm_get_state()
364 unsigned long rate = clk_get_rate(atmel_pwm->clk); in atmel_pwm_get_state()
370 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, in atmel_pwm_get_state()
371 atmel_pwm->data->regs.period); in atmel_pwm_get_state()
374 state->period = DIV64_U64_ROUND_UP(tmp, rate); in atmel_pwm_get_state()
377 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm); in atmel_pwm_get_state()
379 cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, in atmel_pwm_get_state()
380 atmel_pwm->data->regs.duty); in atmel_pwm_get_state()
381 tmp = (u64)(cprd - cdty) * NSEC_PER_SEC; in atmel_pwm_get_state()
383 state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate); in atmel_pwm_get_state()
385 state->enabled = true; in atmel_pwm_get_state()
387 state->enabled = false; in atmel_pwm_get_state()
391 state->polarity = PWM_POLARITY_INVERSED; in atmel_pwm_get_state()
393 state->polarity = PWM_POLARITY_NORMAL; in atmel_pwm_get_state()
444 .compatible = "atmel,at91sam9rl-pwm",
447 .compatible = "atmel,sama5d3-pwm",
450 .compatible = "atmel,sama5d2-pwm",
453 .compatible = "microchip,sam9x60-pwm",
472 cnt = bitmap_weight(&sr, chip->npwm); in atmel_pwm_enable_clk_if_on()
478 ret = clk_enable(atmel_pwm->clk); in atmel_pwm_enable_clk_if_on()
481 "failed to enable clock for pwm %pe\n", in atmel_pwm_enable_clk_if_on()
492 while (cnt--) in atmel_pwm_enable_clk_if_on()
493 clk_disable(atmel_pwm->clk); in atmel_pwm_enable_clk_if_on()
504 chip = devm_pwmchip_alloc(&pdev->dev, 4, sizeof(*atmel_pwm)); in atmel_pwm_probe()
509 atmel_pwm->data = of_device_get_match_data(&pdev->dev); in atmel_pwm_probe()
511 atmel_pwm->update_pending = 0; in atmel_pwm_probe()
512 spin_lock_init(&atmel_pwm->lock); in atmel_pwm_probe()
514 atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0); in atmel_pwm_probe()
515 if (IS_ERR(atmel_pwm->base)) in atmel_pwm_probe()
516 return PTR_ERR(atmel_pwm->base); in atmel_pwm_probe()
518 atmel_pwm->clk = devm_clk_get_prepared(&pdev->dev, NULL); in atmel_pwm_probe()
519 if (IS_ERR(atmel_pwm->clk)) in atmel_pwm_probe()
520 return dev_err_probe(&pdev->dev, PTR_ERR(atmel_pwm->clk), in atmel_pwm_probe()
521 "failed to get prepared PWM clock\n"); in atmel_pwm_probe()
523 chip->ops = &atmel_pwm_ops; in atmel_pwm_probe()
529 ret = devm_pwmchip_add(&pdev->dev, chip); in atmel_pwm_probe()
531 dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n"); in atmel_pwm_probe()
545 .name = "atmel-pwm",
552 MODULE_ALIAS("platform:atmel-pwm");
554 MODULE_DESCRIPTION("Atmel PWM driver");