1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8  * - The writes to cycle registers are shadowed until a write to
10  * - If both OFF_CYCLES and ON_CYCLES are set to 0, the output
12  * - When APPLE_PWM_CTRL is set to 0, the output is constant low
47 	struct apple_pwm *fpwm;  in apple_pwm_apply()  local
49 	if (state->polarity == PWM_POLARITY_INVERSED)  in apple_pwm_apply()
50 		return -EINVAL;  in apple_pwm_apply()
52 	fpwm = to_apple_pwm(chip);  in apple_pwm_apply()
53 	if (state->enabled) {  in apple_pwm_apply()
56 		on_cycles = mul_u64_u64_div_u64(fpwm->clkrate,  in apple_pwm_apply()
57 						state->duty_cycle, NSEC_PER_SEC);  in apple_pwm_apply()
61 		off_cycles = mul_u64_u64_div_u64(fpwm->clkrate,  in apple_pwm_apply()
62 						 state->period, NSEC_PER_SEC) - on_cycles;  in apple_pwm_apply()
66 		writel(on_cycles, fpwm->base + APPLE_PWM_ON_CYCLES);  in apple_pwm_apply()
67 		writel(off_cycles, fpwm->base + APPLE_PWM_OFF_CYCLES);  in apple_pwm_apply()
69 		       fpwm->base + APPLE_PWM_CTRL);  in apple_pwm_apply()
71 		writel(0, fpwm->base + APPLE_PWM_CTRL);  in apple_pwm_apply()
79 	struct apple_pwm *fpwm;  in apple_pwm_get_state()  local
82 	fpwm = to_apple_pwm(chip);  in apple_pwm_get_state()
84 	ctrl = readl(fpwm->base + APPLE_PWM_CTRL);  in apple_pwm_get_state()
85 	on_cycles = readl(fpwm->base + APPLE_PWM_ON_CYCLES);  in apple_pwm_get_state()
86 	off_cycles = readl(fpwm->base + APPLE_PWM_OFF_CYCLES);  in apple_pwm_get_state()
88 	state->enabled = (ctrl & APPLE_PWM_CTRL_ENABLE) && (ctrl & APPLE_PWM_CTRL_OUTPUT_ENABLE);  in apple_pwm_get_state()
89 	state->polarity = PWM_POLARITY_NORMAL;  in apple_pwm_get_state()
91 	state->duty_cycle = DIV64_U64_ROUND_UP((u64)on_cycles * NSEC_PER_SEC, fpwm->clkrate);  in apple_pwm_get_state()
92 	state->period = DIV64_U64_ROUND_UP(((u64)off_cycles + (u64)on_cycles) *  in apple_pwm_get_state()
93 					    NSEC_PER_SEC, fpwm->clkrate);  in apple_pwm_get_state()
106 	struct apple_pwm *fpwm;  in apple_pwm_probe()  local
110 	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*fpwm));  in apple_pwm_probe()
114 	fpwm = to_apple_pwm(chip);  in apple_pwm_probe()
116 	fpwm->base = devm_platform_ioremap_resource(pdev, 0);  in apple_pwm_probe()
117 	if (IS_ERR(fpwm->base))  in apple_pwm_probe()
118 		return PTR_ERR(fpwm->base);  in apple_pwm_probe()
120 	clk = devm_clk_get_enabled(&pdev->dev, NULL);  in apple_pwm_probe()
122 		return dev_err_probe(&pdev->dev, PTR_ERR(clk), "unable to get the clock");  in apple_pwm_probe()
130 	fpwm->clkrate = clk_get_rate(clk);  in apple_pwm_probe()
131 	if (fpwm->clkrate > NSEC_PER_SEC)  in apple_pwm_probe()
132 		return dev_err_probe(&pdev->dev, -EINVAL, "pwm clock out of range");  in apple_pwm_probe()
134 	chip->ops = &apple_pwm_ops;  in apple_pwm_probe()
136 	ret = devm_pwmchip_add(&pdev->dev, chip);  in apple_pwm_probe()
138 		return dev_err_probe(&pdev->dev, ret, "unable to add pwm chip");  in apple_pwm_probe()
144 	{ .compatible = "apple,s5l-fpwm" },
152 		.name = "apple-pwm",