Lines Matching +full:0 +full:x01200000
28 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
29 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
31 #define PCI_VENDOR_ID_CELESTICA 0x18d4
32 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
34 #define PCI_VENDOR_ID_OROLIA 0x1ad7
35 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
37 #define PCI_VENDOR_ID_ADVA 0xad5a
38 #define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400
76 #define OCP_CTRL_ENABLE BIT(0)
84 #define OCP_STATUS_IN_SYNC BIT(0)
87 #define OCP_SELECT_CLK_NONE 0
88 #define OCP_SELECT_CLK_REG 0xfe
106 #define TOD_CTRL_ENABLE BIT(0)
107 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
110 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
141 #define PPS_STATUS_FILTER_ERR BIT(0)
164 #define IRIG_M_CTRL_ENABLE BIT(0)
175 #define IRIG_S_CTRL_ENABLE BIT(0)
185 #define DCF_M_CTRL_ENABLE BIT(0)
195 #define DCF_S_CTRL_ENABLE BIT(0)
229 #define FREQ_STATUS_MASK GENMASK(23, 0)
296 #define OCP_CAP_BASIC BIT(0)
391 #define OCP_REQ_TIMESTAMP BIT(0)
445 { EEPROM_ENTRY(0x43, board_id) },
446 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
451 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
452 { EEPROM_ENTRY(0x200 + 0x63, serial) },
480 * 0: PPS (TS5)
509 .offset = 0x01000000, .size = 0x10000,
513 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
515 .index = 0,
522 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
531 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
540 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
549 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
559 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
567 OCP_EXT_RESOURCE(signal_out[0]),
568 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
577 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
586 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
595 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
604 .offset = 0x01030000, .size = 0x10000,
608 .offset = 0x01040000, .size = 0x10000,
612 .offset = 0x01050000, .size = 0x10000,
616 .offset = 0x01070000, .size = 0x10000,
620 .offset = 0x01080000, .size = 0x10000,
624 .offset = 0x01090000, .size = 0x10000,
628 .offset = 0x010A0000, .size = 0x10000,
632 .offset = 0x010B0000, .size = 0x10000,
636 .offset = 0x00020000, .size = 0x1000,
640 .offset = 0x00130000, .size = 0x1000,
644 .offset = 0x00140000, .size = 0x1000,
648 .offset = 0x00220000, .size = 0x1000,
652 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
660 { I2C_BOARD_INFO("24c02", 0x50) },
661 { I2C_BOARD_INFO("24mac402", 0x58),
669 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
676 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
683 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
690 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
694 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
696 .name = "xilinx_spi", .pci_offset = 0,
710 OCP_MEM_RESOURCE(freq_in[0]),
711 .offset = 0x01200000, .size = 0x10000,
715 .offset = 0x01210000, .size = 0x10000,
719 .offset = 0x01220000, .size = 0x10000,
723 .offset = 0x01230000, .size = 0x10000,
728 .servo_offset_p = 0x2000,
729 .servo_offset_i = 0x1000,
730 .servo_drift_p = 0,
731 .servo_drift_i = 0,
750 .offset = 0x01000000, .size = 0x10000,
754 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
761 .offset = 0x003C0000, .size = 0x1000,
766 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
768 .index = 0,
775 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
784 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
793 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
802 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
812 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
821 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
823 .name = "spi_altera", .pci_offset = 0,
836 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
846 I2C_BOARD_INFO("24c08", 0x50),
853 .offset = 0x00190000, .irq_vec = 7,
860 .offset = 0x210000, .size = 0x1000,
865 .servo_offset_p = 0x2000,
866 .servo_offset_i = 0x1000,
867 .servo_drift_p = 0,
868 .servo_drift_i = 0,
877 .offset = 0x01000000, .size = 0x10000,
881 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
883 .index = 0,
890 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
899 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
909 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
917 OCP_EXT_RESOURCE(signal_out[0]),
918 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
927 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
936 .offset = 0x01030000, .size = 0x10000,
940 .offset = 0x01040000, .size = 0x10000,
944 .offset = 0x01050000, .size = 0x10000,
948 .offset = 0x00020000, .size = 0x1000,
952 .offset = 0x00130000, .size = 0x1000,
956 .offset = 0x00140000, .size = 0x1000,
960 .offset = 0x00220000, .size = 0x1000,
964 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
971 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
977 OCP_MEM_RESOURCE(freq_in[0]),
978 .offset = 0x01200000, .size = 0x10000,
982 .offset = 0x01210000, .size = 0x10000,
986 .offset = 0x00310400, .size = 0x10000, .irq_vec = 9,
988 .name = "spi_altera", .pci_offset = 0,
1001 .offset = 0x150000, .size = 0x100, .irq_vec = 7,
1013 { I2C_BOARD_INFO("24c02", 0x50) },
1014 { I2C_BOARD_INFO("24mac402", 0x58),
1023 .servo_offset_p = 0xc000,
1024 .servo_offset_i = 0x1000,
1025 .servo_drift_p = 0,
1026 .servo_drift_i = 0,
1051 { .name = "NONE", .value = 0 },
1058 { .name = "REGS", .value = 0xfe },
1059 { .name = "EXT", .value = 0xff },
1065 #define SMA_SELECT_MASK GENMASK(14, 0)
1068 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1069 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1070 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1071 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1072 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1073 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1074 { .name = "DCF", .value = 0x0020, .frequency = 77500 },
1075 { .name = "TS3", .value = 0x0040, .frequency = 0 },
1076 { .name = "TS4", .value = 0x0080, .frequency = 0 },
1077 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1078 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1079 { .name = "FREQ3", .value = 0x0400, .frequency = 0 },
1080 { .name = "FREQ4", .value = 0x0800, .frequency = 0 },
1081 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1086 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1087 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1088 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1089 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1090 { .name = "GNSS2", .value = 0x0008, .frequency = 1 },
1091 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1092 { .name = "DCF", .value = 0x0020, .frequency = 77000 },
1093 { .name = "GEN1", .value = 0x0040 },
1094 { .name = "GEN2", .value = 0x0080 },
1095 { .name = "GEN3", .value = 0x0100 },
1096 { .name = "GEN4", .value = 0x0200 },
1097 { .name = "GND", .value = 0x2000 },
1098 { .name = "VCC", .value = 0x4000 },
1103 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1104 { .name = "10Mhz", .value = 0x0008, .frequency = 1000000 },
1109 { .name = "PHC", .value = 0x0002, .frequency = 1 },
1110 { .name = "GNSS", .value = 0x0004, .frequency = 1 },
1111 { .name = "10Mhz", .value = 0x0010, .frequency = 10000000 },
1116 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1117 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1118 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1119 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1120 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1121 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1122 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1123 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1128 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1129 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1130 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1131 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1132 { .name = "GEN1", .value = 0x0040 },
1133 { .name = "GEN2", .value = 0x0080 },
1134 { .name = "GND", .value = 0x2000 },
1135 { .name = "VCC", .value = 0x4000 },
1176 for (i = 0; tbl[i].name; i++) in ptp_ocp_select_name_from_val()
1188 for (i = 0; tbl[i].name; i++) { in ptp_ocp_select_val_from_name()
1202 count = 0; in ptp_ocp_select_table_show()
1203 for (i = 0; tbl[i].name; i++) in ptp_ocp_select_table_show()
1223 for (i = 0; i < 100; i++) { in __ptp_ocp_gettime_locked()
1242 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT; in __ptp_ocp_gettime_locked()
1292 return 0; in ptp_ocp_settime()
1339 return 0; in ptp_ocp_adjtime()
1342 sign = delta_ns < 0 ? BIT(31) : 0; in ptp_ocp_adjtime()
1349 return 0; in ptp_ocp_adjtime()
1355 if (scaled_ppm == 0) in ptp_ocp_null_adjfine()
1356 return 0; in ptp_ocp_null_adjfine()
1364 return 0; in ptp_ocp_null_getmaxphase()
1386 case 0: in ptp_ocp_enable()
1412 case 0: in ptp_ocp_enable()
1417 rq->perout.period.nsec != 0)) in ptp_ocp_enable()
1419 return 0; in ptp_ocp_enable()
1456 return 0; in ptp_ocp_verify()
1458 /* channel 0 is 1PPS from PHC. in ptp_ocp_verify()
1500 iowrite32(0, &bp->reg->drift_ns); in __ptp_ocp_clear_drift_locked()
1547 bp->gnss_lost = 0; in ptp_ocp_watchdog()
1571 for (i = 0; i < 3; i++) { in ptp_ocp_estimate_pci_timing()
1607 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) { in ptp_ocp_init_clock()
1622 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0); in ptp_ocp_init_clock()
1626 return 0; in ptp_ocp_init_clock()
1687 return 0; in ptp_ocp_nvmem_match()
1692 return 0; in ptp_ocp_nvmem_match()
1786 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1794 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1803 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1807 crc = crc16(0xffff, &fw->data[offset], length); in ptp_ocp_devlink_fw_image()
1811 NULL, 0, 0); in ptp_ocp_devlink_fw_image()
1818 return 0; in ptp_ocp_devlink_fw_image()
1837 off = 0; in ptp_ocp_devlink_flash()
1882 NULL, 0, 0); in ptp_ocp_devlink_flash_update()
1887 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0); in ptp_ocp_devlink_flash_update()
1911 return 0; in ptp_ocp_devlink_info_get()
1925 return 0; in ptp_ocp_devlink_info_get()
1946 start = pci_resource_start(bp->pdev, 0) + r->offset; in ptp_ocp_get_mem()
1960 start = pci_resource_start(pdev, 0) + r->offset; in ptp_ocp_register_spi()
1961 res[0] = DEFINE_RES_MEM(start, r->size); in ptp_ocp_register_spi()
1976 return 0; in ptp_ocp_register_spi()
1987 start = pci_resource_start(pdev, 0) + r->offset; in ptp_ocp_i2c_bus()
1988 res[0] = DEFINE_RES_MEM(start, r->size); in ptp_ocp_i2c_bus()
2010 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0, in ptp_ocp_register_i2c()
2024 return 0; in ptp_ocp_register_i2c()
2044 iowrite32(0, ®->intr_mask); in ptp_ocp_signal_irq()
2045 iowrite32(0, ®->enable); in ptp_ocp_signal_irq()
2049 iowrite32(0, ®->intr); /* ack interrupt */ in ptp_ocp_signal_irq()
2063 return 0; in ptp_ocp_signal_set()
2091 return 0; in ptp_ocp_signal_set()
2103 return 0; in ptp_ocp_signal_from_perout()
2129 iowrite32(0, ®->intr_mask); in ptp_ocp_signal_enable()
2130 iowrite32(0, ®->enable); in ptp_ocp_signal_enable()
2133 return 0; in ptp_ocp_signal_enable()
2148 iowrite32(0, ®->repeat_count); in ptp_ocp_signal_enable()
2150 iowrite32(0, ®->intr); /* clear interrupt state */ in ptp_ocp_signal_enable()
2156 return 0; in ptp_ocp_signal_enable()
2173 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0) in ptp_ocp_ts_irq()
2209 if ((!!old_map ^ !!bp->pps_req_map) == 0) in ptp_ocp_ts_enable()
2210 return 0; in ptp_ocp_ts_enable()
2218 iowrite32(0, ®->intr_mask); in ptp_ocp_ts_enable()
2219 iowrite32(0, ®->enable); in ptp_ocp_ts_enable()
2222 return 0; in ptp_ocp_ts_enable()
2228 ext->info->enable(ext, ~0, false); in ptp_ocp_unregister_ext()
2263 return 0; in ptp_ocp_register_ext()
2279 memset(&uart, 0, sizeof(uart)); in ptp_ocp_serial_line()
2283 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset; in ptp_ocp_serial_line()
2299 if (port.line < 0) in ptp_ocp_register_serial()
2307 return 0; in ptp_ocp_register_serial()
2321 return 0; in ptp_ocp_register_mem()
2330 iowrite32(0, &bp->nmea_out->ctrl); /* disable */ in ptp_ocp_nmea_out_init()
2340 iowrite32(0, ®->enable); /* disable */ in _ptp_ocp_signal_init()
2352 for (i = 0; i < 4; i++) in ptp_ocp_signal_init()
2372 count = 0; in ptp_ocp_attr_group_add()
2373 for (i = 0; attr_tbl[i].cap; i++) in ptp_ocp_attr_group_add()
2382 count = 0; in ptp_ocp_attr_group_add()
2383 for (i = 0; attr_tbl[i].cap; i++) in ptp_ocp_attr_group_add()
2389 bp->attr_group[0] = NULL; in ptp_ocp_attr_group_add()
2404 ctrl |= enable ? bit : 0; in ptp_ocp_enable_fpga()
2440 ptp_ocp_irig_out(bp, val & 0x00100010); in __handle_signal_outputs()
2441 ptp_ocp_dcf_out(bp, val & 0x00200020); in __handle_signal_outputs()
2447 ptp_ocp_irig_in(bp, val & 0x00100010); in __handle_signal_inputs()
2448 ptp_ocp_dcf_in(bp, val & 0x00200020); in __handle_signal_inputs()
2464 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_fb_get()
2466 return (ioread32(gpio) >> shift) & 0xffff; in ptp_ocp_sma_fb_get()
2477 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_fb_set_output()
2479 mask = 0xffff << (16 - shift); in ptp_ocp_sma_fb_set_output()
2492 return 0; in ptp_ocp_sma_fb_set_output()
2503 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_fb_set_inputs()
2505 mask = 0xffff << (16 - shift); in ptp_ocp_sma_fb_set_inputs()
2518 return 0; in ptp_ocp_sma_fb_set_inputs()
2536 for (i = 0; i < OCP_SMA_NUM; i++) { in ptp_ocp_sma_fb_init()
2542 bp->sma[0].mode = SMA_MODE_IN; in ptp_ocp_sma_fb_init()
2548 for (i = 0; i < OCP_SMA_NUM; i++) { in ptp_ocp_sma_fb_init()
2561 if (reg == 0xffffffff) { in ptp_ocp_sma_fb_init()
2562 for (i = 0; i < OCP_SMA_NUM; i++) in ptp_ocp_sma_fb_init()
2566 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT; in ptp_ocp_sma_fb_init()
2591 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_adva_set_output()
2593 mask = 0xffff << (16 - shift); in ptp_ocp_sma_adva_set_output()
2604 return 0; in ptp_ocp_sma_adva_set_output()
2615 shift = sma_nr & 1 ? 0 : 16; in ptp_ocp_sma_adva_set_inputs()
2617 mask = 0xffff << (16 - shift); in ptp_ocp_sma_adva_set_inputs()
2628 return 0; in ptp_ocp_sma_adva_set_inputs()
2649 for (i = 0; i < 4; i++) { in ptp_ocp_set_pins()
2657 return 0; in ptp_ocp_set_pins()
2669 if ((version & 0xffff) == 0) { in ptp_ocp_fb_set_version()
2675 bp->fw_version = version & 0x7fff; in ptp_ocp_fb_set_version()
2738 int err = 0; in ptp_ocp_register_resources()
2761 .capabilities = 0, in ptp_ocp_art_sma_init()
2770 bp->sma[0].mode = SMA_MODE_IN; in ptp_ocp_art_sma_init()
2775 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */ in ptp_ocp_art_sma_init()
2776 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */ in ptp_ocp_art_sma_init()
2777 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */ in ptp_ocp_art_sma_init()
2778 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */ in ptp_ocp_art_sma_init()
2780 for (i = 0; i < OCP_SMA_NUM; i++) { in ptp_ocp_art_sma_init()
2792 switch (reg & 0xff) { in ptp_ocp_art_sma_init()
2793 case 0: in ptp_ocp_art_sma_init()
2818 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff; in ptp_ocp_art_sma_get()
2821 /* note: store 0 is considered invalid. */
2827 int err = 0; in ptp_ocp_art_sma_set()
2838 if (((reg >> 16) & val) == 0) { in ptp_ocp_art_sma_set()
2841 reg = (reg & 0xff00) | (val & 0xff); in ptp_ocp_art_sma_set()
2863 bp->flash_start = 0x1000000; in ptp_ocp_art_board_init()
2894 bp->flash_start = 0xA00000; in ptp_ocp_adva_board_init()
2902 if ((version & 0xffff) == 0) { in ptp_ocp_adva_board_init()
2907 bp->fw_version = version & 0xffff; in ptp_ocp_adva_board_init()
2950 for (i = 0; tbl[i].name; i++) { in ptp_ocp_show_inputs()
2956 if (!val && def_val >= 0) { in ptp_ocp_show_inputs()
2982 idx = 0; in sma_parse_inputs()
2983 dir = *mode == SMA_MODE_IN ? 0 : 1; in sma_parse_inputs()
2984 if (!strcasecmp("IN:", argv[0])) { in sma_parse_inputs()
2985 dir = 0; in sma_parse_inputs()
2988 if (!strcasecmp("OUT:", argv[0])) { in sma_parse_inputs()
2992 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT; in sma_parse_inputs()
2994 ret = 0; in sma_parse_inputs()
2997 if (ret < 0) in sma_parse_inputs()
3019 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val); in ptp_ocp_sma_show()
3030 return ptp_ocp_sma_show(bp, 1, buf, 0, 1); in sma1_show()
3046 return ptp_ocp_sma_show(bp, 3, buf, -1, 0); in sma3_show()
3068 return 0; in ptp_ocp_sma_store_val()
3075 ptp_ocp_sma_set_output(bp, sma_nr, 0); in ptp_ocp_sma_store_val()
3077 ptp_ocp_sma_set_inputs(bp, sma_nr, 0); in ptp_ocp_sma_store_val()
3085 val = 0; in ptp_ocp_sma_store_val()
3104 if (val < 0) in ptp_ocp_sma_store()
3163 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf); in available_sma_inputs_show()
3216 err = kstrtou64(argv[argc], 0, &s.phase); in signal_store()
3222 err = kstrtoint(argv[argc], 0, &s.duty); in signal_store()
3228 err = kstrtou64(argv[argc], 0, &s.period); in signal_store()
3240 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0); in signal_store()
3268 static EXT_ATTR_RW(signal, signal, 0);
3282 static EXT_ATTR_RO(signal, duty, 0);
3296 static EXT_ATTR_RO(signal, period, 0);
3310 static EXT_ATTR_RO(signal, phase, 0);
3325 static EXT_ATTR_RO(signal, polarity, 0);
3339 static EXT_ATTR_RO(signal, running, 0);
3355 static EXT_ATTR_RO(signal, start, 0);
3370 err = kstrtou32(buf, 0, &val); in seconds_store()
3373 if (val > 0xff) in seconds_store()
3377 val = (val << 8) | 0x1; in seconds_store()
3394 val = (val >> 8) & 0xff; in seconds_show()
3396 val = 0; in seconds_show()
3400 static EXT_ATTR_RW(freq, seconds, 0);
3420 return 0; in frequency_show()
3422 static EXT_ATTR_RO(freq, frequency, 0);
3450 return port->line == -1 ? 0 : 0444; in ptp_ocp_timecard_tty_is_visible()
3520 err = kstrtou32(buf, 0, &val); in utc_tai_offset_store()
3548 err = kstrtou32(buf, 0, &val); in ts_window_adjust_store()
3565 val = (val >> 16) & 0x07; in irig_b_mode_show()
3580 err = kstrtou8(buf, 0, &val); in irig_b_mode_store()
3586 reg = ((val & 0x7) << 16); in irig_b_mode_store()
3589 iowrite32(0, &bp->irig_out->ctrl); /* disable */ in irig_b_mode_store()
3620 if (val < 0) in clock_source_store()
3690 u32 val = 0; in tod_correction_store()
3692 err = kstrtos32(buf, 0, &res); in tod_correction_store()
3695 if (res < 0) { in tod_correction_store()
3729 DEVICE_SIGNAL_GROUP(gen1, 0);
3749 DEVICE_FREQ_GROUP(freq1, 0);
3769 err = 0; in disciplining_config_read()
3806 err = nvmem_device_write(nvmem, 0x00, count, buf); in disciplining_config_write()
3831 err = 0; in temperature_table_read()
3839 err = nvmem_device_read(nvmem, 0x90 + off, count, buf); in temperature_table_read()
3868 err = nvmem_device_write(nvmem, 0x90, count, buf); in temperature_table_write()
3986 for (i = 0; i < 4; i++) { in gpio_input_map()
3989 if (map[i][0] & (1 << bit)) { in gpio_input_map()
4006 for (i = 0; i < 4; i++) { in gpio_output_map()
4052 val = (val >> 8) & 0xff; in _frequency_summary_show()
4089 for (i = 0; i < __PORT_COUNT; i++) { in ptp_ocp_summary_show()
4095 memset(sma_val, 0xff, sizeof(sma_val)); in ptp_ocp_summary_show()
4100 sma_val[0][0] = reg & 0xffff; in ptp_ocp_summary_show()
4101 sma_val[1][0] = reg >> 16; in ptp_ocp_summary_show()
4104 sma_val[2][1] = reg & 0xffff; in ptp_ocp_summary_show()
4108 sma_val[2][0] = reg & 0xffff; in ptp_ocp_summary_show()
4109 sma_val[3][0] = reg >> 16; in ptp_ocp_summary_show()
4112 sma_val[0][1] = reg & 0xffff; in ptp_ocp_summary_show()
4118 sma_val[0][0], sma_val[0][1], buf); in ptp_ocp_summary_show()
4122 sma_val[1][0], sma_val[1][1], buf); in ptp_ocp_summary_show()
4126 sma_val[2][0], sma_val[2][1], buf); in ptp_ocp_summary_show()
4130 sma_val[3][0], sma_val[3][1], buf); in ptp_ocp_summary_show()
4186 for (i = 0; i < bp->signals_nr; i++) in ptp_ocp_summary_show()
4190 for (i = 0; i < bp->freq_in_nr; i++) in ptp_ocp_summary_show()
4238 if (val & 0x01) { in ptp_ocp_summary_show()
4239 gpio_input_map(src, bp, sma_val, 0, NULL); in ptp_ocp_summary_show()
4241 } else if (val & 0x02) { in ptp_ocp_summary_show()
4243 } else if (val & 0x04) { in ptp_ocp_summary_show()
4261 case 0: in ptp_ocp_summary_show()
4301 return 0; in ptp_ocp_summary_show()
4318 return 0; in ptp_ocp_tod_status_show()
4320 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val); in ptp_ocp_tod_status_show()
4322 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0; in ptp_ocp_tod_status_show()
4331 val >> 24, (val >> 16) & 0xff, val & 0xffff); in ptp_ocp_tod_status_show()
4334 seq_printf(s, "Status register: 0x%08X\n", val); in ptp_ocp_tod_status_show()
4342 seq_printf(s, "UTC status register: 0x%08X\n", val); in ptp_ocp_tod_status_show()
4344 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0); in ptp_ocp_tod_status_show()
4346 val & TOD_STATUS_LEAP_VALID ? 1 : 0, in ptp_ocp_tod_status_show()
4347 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0); in ptp_ocp_tod_status_show()
4352 return 0; in ptp_ocp_tod_status_show()
4406 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL); in ptp_ocp_device_init()
4408 if (err < 0) { in ptp_ocp_device_init()
4417 for (i = 0; i < __PORT_COUNT; i++) in ptp_ocp_device_init()
4437 return 0; in ptp_ocp_device_init()
4485 return 0; in ptp_ocp_complete()
4497 version >> 24, (version >> 16) & 0xff, version & 0xffff, in ptp_ocp_phc_info()
4528 for (i = 0; i < __PORT_COUNT; i++) { in ptp_ocp_info()
4571 for (i = 0; i < 4; i++) in ptp_ocp_detach()
4574 for (i = 0; i < __PORT_COUNT; i++) in ptp_ocp_detach()
4599 return 0; in ptp_ocp_dpll_lock_status_get()
4614 return 0; in ptp_ocp_dpll_state_get()
4624 return 0; in ptp_ocp_dpll_mode_get()
4639 return 0; in ptp_ocp_dpll_direction_get()
4658 return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr + 1); in ptp_ocp_dpll_direction_set()
4677 for (i = 0; tbl[i].name; i++) in ptp_ocp_dpll_frequency_set()
4698 for (i = 0; tbl[i].name; i++) in ptp_ocp_dpll_frequency_get()
4701 return 0; in ptp_ocp_dpll_frequency_get()
4770 if (err < 0) { in ptp_ocp_probe()
4797 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE); in ptp_ocp_probe()
4808 for (i = 0; i < OCP_SMA_NUM; i++) { in ptp_ocp_probe()
4824 return 0; in ptp_ocp_probe()
4849 for (i = 0; i < OCP_SMA_NUM; i++) { in ptp_ocp_remove()
4885 return 0; in ptp_ocp_i2c_notifier_call()
4889 return 0; in ptp_ocp_i2c_notifier_call()
4895 return 0; in ptp_ocp_i2c_notifier_call()
4904 return 0; in ptp_ocp_i2c_notifier_call()
4934 return 0; in ptp_ocp_init()