Lines Matching +full:ptp +full:- +full:ref
1 // SPDX-License-Identifier: GPL-2.0
25 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
46 return regmap_bulk_read(idt82p33->regmap, regaddr, buf, count); in idt82p33_read()
52 return regmap_bulk_write(idt82p33->regmap, regaddr, buf, count); in idt82p33_write()
65 nsec |= buf[2 - i]; in idt82p33_byte_array_to_timespec()
71 sec |= buf[8 - i]; in idt82p33_byte_array_to_timespec()
74 ts->tv_sec = sec; in idt82p33_byte_array_to_timespec()
75 ts->tv_nsec = nsec; in idt82p33_byte_array_to_timespec()
85 nsec = ts->tv_nsec; in idt82p33_timespec_to_byte_array()
86 sec = ts->tv_sec; in idt82p33_timespec_to_byte_array()
102 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_dpll_set_mode()
106 if (channel->pll_mode == mode) in idt82p33_dpll_set_mode()
109 err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg, in idt82p33_dpll_set_mode()
118 err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg, in idt82p33_dpll_set_mode()
123 channel->pll_mode = mode; in idt82p33_dpll_set_mode()
131 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_set_tod_trigger()
136 return -EINVAL; in idt82p33_set_tod_trigger()
138 err = idt82p33_read(idt82p33, channel->dpll_tod_trigger, in idt82p33_set_tod_trigger()
151 return idt82p33_write(idt82p33, channel->dpll_tod_trigger, in idt82p33_set_tod_trigger()
158 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_get_extts()
162 err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf)); in idt82p33_get_extts()
168 if (memcmp(buf, channel->extts_tod_sts, TOD_BYTE_COUNT) == 0) in idt82p33_get_extts()
169 return -EAGAIN; in idt82p33_get_extts()
171 memcpy(channel->extts_tod_sts, buf, TOD_BYTE_COUNT); in idt82p33_get_extts()
175 if (channel->discard_next_extts) { in idt82p33_get_extts()
176 channel->discard_next_extts = false; in idt82p33_get_extts()
177 return -EAGAIN; in idt82p33_get_extts()
183 static int map_ref_to_tod_trig_sel(int ref, u8 *trigger) in map_ref_to_tod_trig_sel() argument
187 switch (ref) { in map_ref_to_tod_trig_sel()
198 err = -EINVAL; in map_ref_to_tod_trig_sel()
215 struct idt82p33 *idt82p33 = channel->idt82p33; in arm_tod_read_with_trigger()
220 err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf)); in arm_tod_read_with_trigger()
225 memcpy(channel->extts_tod_sts, buf, TOD_BYTE_COUNT); in arm_tod_read_with_trigger()
230 dev_err(idt82p33->dev, "%s: err = %d", __func__, err); in arm_tod_read_with_trigger()
238 u8 index = rq->extts.index; in idt82p33_extts_enable()
244 int ref; in idt82p33_extts_enable() local
246 idt82p33 = channel->idt82p33; in idt82p33_extts_enable()
247 old_mask = idt82p33->extts_mask; in idt82p33_extts_enable()
250 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | in idt82p33_extts_enable()
254 return -EOPNOTSUPP; in idt82p33_extts_enable()
257 if ((rq->extts.flags & PTP_ENABLE_FEATURE) && in idt82p33_extts_enable()
258 (rq->extts.flags & PTP_FALLING_EDGE)) in idt82p33_extts_enable()
259 return -EOPNOTSUPP; in idt82p33_extts_enable()
262 return -EINVAL; in idt82p33_extts_enable()
266 if (idt82p33->extts_mask & mask) in idt82p33_extts_enable()
270 ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->plln); in idt82p33_extts_enable()
272 if (ref < 0) { in idt82p33_extts_enable()
273 dev_err(idt82p33->dev, "%s: No valid pin found for Pll%d!\n", in idt82p33_extts_enable()
274 __func__, channel->plln); in idt82p33_extts_enable()
275 return -EBUSY; in idt82p33_extts_enable()
278 err = map_ref_to_tod_trig_sel(ref, &trigger); in idt82p33_extts_enable()
281 dev_err(idt82p33->dev, in idt82p33_extts_enable()
282 "%s: Unsupported ref %d!\n", __func__, ref); in idt82p33_extts_enable()
286 err = arm_tod_read_with_trigger(&idt82p33->channel[index], trigger); in idt82p33_extts_enable()
289 idt82p33->extts_mask |= mask; in idt82p33_extts_enable()
290 idt82p33->channel[index].tod_trigger = trigger; in idt82p33_extts_enable()
291 idt82p33->event_channel[index] = channel; in idt82p33_extts_enable()
292 idt82p33->extts_single_shot = is_one_shot(idt82p33->extts_mask); in idt82p33_extts_enable()
297 schedule_delayed_work(&idt82p33->extts_work, in idt82p33_extts_enable()
301 idt82p33->extts_mask &= ~mask; in idt82p33_extts_enable()
302 idt82p33->extts_single_shot = is_one_shot(idt82p33->extts_mask); in idt82p33_extts_enable()
304 if (idt82p33->extts_mask == 0) in idt82p33_extts_enable()
305 cancel_delayed_work(&idt82p33->extts_work); in idt82p33_extts_enable()
318 err = idt82p33_get_extts(&idt82p33->channel[todn], &ts); in idt82p33_extts_check_channel()
320 event_channel = idt82p33->event_channel[todn]; in idt82p33_extts_check_channel()
324 ptp_clock_event(event_channel->ptp_clock, in idt82p33_extts_check_channel()
333 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_extts_enable_mask()
334 u8 trigger = channel->tod_trigger; in idt82p33_extts_enable_mask()
343 cancel_delayed_work_sync(&idt82p33->extts_work); in idt82p33_extts_enable_mask()
352 err = arm_tod_read_with_trigger(&idt82p33->channel[i], trigger); in idt82p33_extts_enable_mask()
354 dev_err(idt82p33->dev, in idt82p33_extts_enable_mask()
359 if (err == 0 && idt82p33->extts_single_shot) in idt82p33_extts_enable_mask()
360 /* trigger happened so we won't re-enable it */ in idt82p33_extts_enable_mask()
366 schedule_delayed_work(&idt82p33->extts_work, in idt82p33_extts_enable_mask()
375 struct idt82p33 *idt82p33 = channel->idt82p33; in _idt82p33_gettime()
376 u8 old_mask = idt82p33->extts_mask; in _idt82p33_gettime()
390 channel->discard_next_extts = true; in _idt82p33_gettime()
392 if (idt82p33->calculate_overhead_flag) in _idt82p33_gettime()
393 idt82p33->start_time = ktime_get_raw(); in _idt82p33_gettime()
395 err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf)); in _idt82p33_gettime()
400 /* Re-enable extts */ in _idt82p33_gettime()
418 struct idt82p33 *idt82p33 = channel->idt82p33; in _idt82p33_settime()
430 channel->discard_next_extts = true; in _idt82p33_settime()
432 if (idt82p33->calculate_overhead_flag) { in _idt82p33_settime()
434 - ktime_to_ns(idt82p33->start_time); in _idt82p33_settime()
438 idt82p33->calculate_overhead_flag = 0; in _idt82p33_settime()
447 err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i, in _idt82p33_settime()
459 struct idt82p33 *idt82p33 = channel->idt82p33; in _idt82p33_adjtime_immediate()
464 idt82p33->calculate_overhead_flag = 1; in _idt82p33_adjtime_immediate()
472 now_ns += delta_ns + idt82p33->tod_write_overhead_ns; in _idt82p33_adjtime_immediate()
484 struct idt82p33 *idt82p33 = channel->idt82p33; in _idt82p33_adjtime_internal_triggered()
497 if (ts.tv_nsec > (NSEC_PER_SEC - 5 * NSEC_PER_MSEC)) { in _idt82p33_adjtime_internal_triggered()
510 err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg, buf, sizeof(buf)); in _idt82p33_adjtime_internal_triggered()
517 schedule_delayed_work(&channel->adjtime_work, HZ); in _idt82p33_adjtime_internal_triggered()
527 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_adjtime_workaround()
529 mutex_lock(idt82p33->lock); in idt82p33_adjtime_workaround()
530 /* Workaround for TOD-to-output alignment issue */ in idt82p33_adjtime_workaround()
532 mutex_unlock(idt82p33->lock); in idt82p33_adjtime_workaround()
537 struct idt82p33 *idt82p33 = channel->idt82p33; in _idt82p33_adjfine()
543 * Frequency Control Word unit is: 1.6861512 * 10^-10 ppm in _idt82p33_adjfine()
547 * FCW = ----------- in _idt82p33_adjfine()
552 * FCW = ------------------------ in _idt82p33_adjfine()
569 err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg, in _idt82p33_adjfine()
585 else if (current_ppm < -max_scaled_ppm) in idt82p33_ddco_scaled_ppm()
586 current_ppm = -max_scaled_ppm; in idt82p33_ddco_scaled_ppm()
595 err = _idt82p33_adjfine(channel, channel->current_freq); in idt82p33_stop_ddco()
599 channel->ddco = false; in idt82p33_stop_ddco()
606 s32 current_ppm = channel->current_freq; in idt82p33_start_ddco()
631 ptp_schedule_worker(channel->ptp_clock, in idt82p33_start_ddco()
632 msecs_to_jiffies(duration_ms) - 1); in idt82p33_start_ddco()
633 channel->ddco = true; in idt82p33_start_ddco()
641 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_measure_one_byte_write_overhead()
655 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger, in idt82p33_measure_one_byte_write_overhead()
663 total_ns += ktime_to_ns(stop) - ktime_to_ns(start); in idt82p33_measure_one_byte_write_overhead()
674 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_measure_one_byte_read_overhead()
688 err = idt82p33_read(idt82p33, channel->dpll_tod_trigger, in idt82p33_measure_one_byte_read_overhead()
696 total_ns += ktime_to_ns(stop) - ktime_to_ns(start); in idt82p33_measure_one_byte_read_overhead()
707 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_measure_tod_write_9_byte_overhead()
715 idt82p33->tod_write_overhead_ns = 0; in idt82p33_measure_tod_write_9_byte_overhead()
722 for (j = 0; j < (TOD_BYTE_COUNT - 1); j++) { in idt82p33_measure_tod_write_9_byte_overhead()
724 channel->dpll_tod_cnfg + i, in idt82p33_measure_tod_write_9_byte_overhead()
732 total_ns += ktime_to_ns(stop) - ktime_to_ns(start); in idt82p33_measure_tod_write_9_byte_overhead()
735 idt82p33->tod_write_overhead_ns = div_s64(total_ns, in idt82p33_measure_tod_write_9_byte_overhead()
758 *overhead_ns = timespec64_to_ns(&ts2) - timespec64_to_ns(&ts1); in idt82p33_measure_settime_gettime_gap_overhead()
766 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_measure_tod_write_overhead()
769 idt82p33->tod_write_overhead_ns = 0; in idt82p33_measure_tod_write_overhead()
774 dev_err(idt82p33->dev, in idt82p33_measure_tod_write_overhead()
796 trailing_overhead_ns = gap_ns - 2 * one_byte_write_ns in idt82p33_measure_tod_write_overhead()
797 - one_byte_read_ns; in idt82p33_measure_tod_write_overhead()
799 idt82p33->tod_write_overhead_ns -= trailing_overhead_ns; in idt82p33_measure_tod_write_overhead()
813 dev_err(idt82p33->dev, in idt82p33_check_and_set_masks()
815 err = -EINVAL; in idt82p33_check_and_set_masks()
817 idt82p33->pll_mask = val; in idt82p33_check_and_set_masks()
821 idt82p33->channel[0].output_mask = val; in idt82p33_check_and_set_masks()
824 idt82p33->channel[1].output_mask = val; in idt82p33_check_and_set_masks()
834 dev_info(idt82p33->dev, in idt82p33_display_masks()
835 "pllmask = 0x%02x\n", idt82p33->pll_mask); in idt82p33_display_masks()
840 if (mask & idt82p33->pll_mask) in idt82p33_display_masks()
841 dev_info(idt82p33->dev, in idt82p33_display_masks()
843 i, idt82p33->channel[i].output_mask); in idt82p33_display_masks()
849 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_sync_tod()
853 err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg, in idt82p33_sync_tod()
862 return idt82p33_write(idt82p33, channel->dpll_sync_cnfg, in idt82p33_sync_tod()
866 static long idt82p33_work_handler(struct ptp_clock_info *ptp) in idt82p33_work_handler() argument
869 container_of(ptp, struct idt82p33_channel, caps); in idt82p33_work_handler()
870 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_work_handler()
872 mutex_lock(idt82p33->lock); in idt82p33_work_handler()
874 mutex_unlock(idt82p33->lock); in idt82p33_work_handler()
877 return -1; in idt82p33_work_handler()
883 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_output_enable()
903 return idt82p33_output_enable(channel, enable, perout->index); in idt82p33_perout_enable()
908 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_enable_tod()
915 dev_err(idt82p33->dev, in idt82p33_enable_tod()
934 channel = &idt82p33->channel[i]; in idt82p33_ptp_clock_unregister_all()
935 cancel_delayed_work_sync(&channel->adjtime_work); in idt82p33_ptp_clock_unregister_all()
936 if (channel->ptp_clock) in idt82p33_ptp_clock_unregister_all()
937 ptp_clock_unregister(channel->ptp_clock); in idt82p33_ptp_clock_unregister_all()
943 static int idt82p33_enable(struct ptp_clock_info *ptp, in idt82p33_enable() argument
947 container_of(ptp, struct idt82p33_channel, caps); in idt82p33_enable()
948 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_enable()
949 int err = -EOPNOTSUPP; in idt82p33_enable()
951 mutex_lock(idt82p33->lock); in idt82p33_enable()
953 switch (rq->type) { in idt82p33_enable()
957 &rq->perout); in idt82p33_enable()
958 /* Only accept a 1-PPS aligned to the second. */ in idt82p33_enable()
959 else if (rq->perout.start.nsec || rq->perout.period.sec != 1 || in idt82p33_enable()
960 rq->perout.period.nsec) in idt82p33_enable()
961 err = -ERANGE; in idt82p33_enable()
964 &rq->perout); in idt82p33_enable()
973 mutex_unlock(idt82p33->lock); in idt82p33_enable()
976 dev_err(idt82p33->dev, in idt82p33_enable()
981 static s32 idt82p33_getmaxphase(__always_unused struct ptp_clock_info *ptp) in idt82p33_getmaxphase() argument
986 static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offset_ns) in idt82p33_adjwritephase() argument
989 container_of(ptp, struct idt82p33_channel, caps); in idt82p33_adjwritephase()
990 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_adjwritephase()
996 offset_regval = div_s64((s64)(-offset_ns) * 1000000000ll, in idt82p33_adjwritephase()
1005 mutex_lock(idt82p33->lock); in idt82p33_adjwritephase()
1009 dev_err(idt82p33->dev, in idt82p33_adjwritephase()
1014 err = idt82p33_write(idt82p33, channel->dpll_phase_cnfg, val, in idt82p33_adjwritephase()
1018 mutex_unlock(idt82p33->lock); in idt82p33_adjwritephase()
1022 static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) in idt82p33_adjfine() argument
1025 container_of(ptp, struct idt82p33_channel, caps); in idt82p33_adjfine()
1026 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_adjfine()
1029 if (channel->ddco == true) in idt82p33_adjfine()
1032 if (scaled_ppm == channel->current_freq) in idt82p33_adjfine()
1035 mutex_lock(idt82p33->lock); in idt82p33_adjfine()
1039 channel->current_freq = scaled_ppm; in idt82p33_adjfine()
1040 mutex_unlock(idt82p33->lock); in idt82p33_adjfine()
1043 dev_err(idt82p33->dev, in idt82p33_adjfine()
1048 static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns) in idt82p33_adjtime() argument
1051 container_of(ptp, struct idt82p33_channel, caps); in idt82p33_adjtime()
1052 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_adjtime()
1055 if (channel->ddco == true) in idt82p33_adjtime()
1056 return -EBUSY; in idt82p33_adjtime()
1058 mutex_lock(idt82p33->lock); in idt82p33_adjtime()
1062 mutex_unlock(idt82p33->lock); in idt82p33_adjtime()
1071 mutex_unlock(idt82p33->lock); in idt82p33_adjtime()
1074 dev_err(idt82p33->dev, in idt82p33_adjtime()
1079 static int idt82p33_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) in idt82p33_gettime() argument
1082 container_of(ptp, struct idt82p33_channel, caps); in idt82p33_gettime()
1083 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_gettime()
1086 mutex_lock(idt82p33->lock); in idt82p33_gettime()
1088 mutex_unlock(idt82p33->lock); in idt82p33_gettime()
1091 dev_err(idt82p33->dev, in idt82p33_gettime()
1096 static int idt82p33_settime(struct ptp_clock_info *ptp, in idt82p33_settime() argument
1100 container_of(ptp, struct idt82p33_channel, caps); in idt82p33_settime()
1101 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_settime()
1104 mutex_lock(idt82p33->lock); in idt82p33_settime()
1106 mutex_unlock(idt82p33->lock); in idt82p33_settime()
1109 dev_err(idt82p33->dev, in idt82p33_settime()
1116 struct idt82p33_channel *channel = &idt82p33->channel[index]; in idt82p33_channel_init()
1120 channel->dpll_tod_cnfg = DPLL1_TOD_CNFG; in idt82p33_channel_init()
1121 channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER; in idt82p33_channel_init()
1122 channel->dpll_tod_sts = DPLL1_TOD_STS; in idt82p33_channel_init()
1123 channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG; in idt82p33_channel_init()
1124 channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG; in idt82p33_channel_init()
1125 channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG; in idt82p33_channel_init()
1126 channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG; in idt82p33_channel_init()
1127 channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG; in idt82p33_channel_init()
1130 channel->dpll_tod_cnfg = DPLL2_TOD_CNFG; in idt82p33_channel_init()
1131 channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER; in idt82p33_channel_init()
1132 channel->dpll_tod_sts = DPLL2_TOD_STS; in idt82p33_channel_init()
1133 channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG; in idt82p33_channel_init()
1134 channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG; in idt82p33_channel_init()
1135 channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG; in idt82p33_channel_init()
1136 channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG; in idt82p33_channel_init()
1137 channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG; in idt82p33_channel_init()
1140 return -EINVAL; in idt82p33_channel_init()
1143 channel->plln = index; in idt82p33_channel_init()
1144 channel->current_freq = 0; in idt82p33_channel_init()
1145 channel->idt82p33 = idt82p33; in idt82p33_channel_init()
1146 INIT_DELAYED_WORK(&channel->adjtime_work, idt82p33_adjtime_workaround); in idt82p33_channel_init()
1151 static int idt82p33_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, in idt82p33_verify_pin() argument
1160 return -1; in idt82p33_verify_pin()
1171 caps->owner = THIS_MODULE; in idt82p33_caps_init()
1172 caps->max_adj = DCO_MAX_PPB; in idt82p33_caps_init()
1173 caps->n_per_out = MAX_PER_OUT; in idt82p33_caps_init()
1174 caps->n_ext_ts = MAX_PHC_PLL; in idt82p33_caps_init()
1175 caps->n_pins = max_pins; in idt82p33_caps_init()
1176 caps->adjphase = idt82p33_adjwritephase; in idt82p33_caps_init()
1177 caps->getmaxphase = idt82p33_getmaxphase; in idt82p33_caps_init()
1178 caps->adjfine = idt82p33_adjfine; in idt82p33_caps_init()
1179 caps->adjtime = idt82p33_adjtime; in idt82p33_caps_init()
1180 caps->gettime64 = idt82p33_gettime; in idt82p33_caps_init()
1181 caps->settime64 = idt82p33_settime; in idt82p33_caps_init()
1182 caps->enable = idt82p33_enable; in idt82p33_caps_init()
1183 caps->verify = idt82p33_verify_pin; in idt82p33_caps_init()
1184 caps->do_aux_work = idt82p33_work_handler; in idt82p33_caps_init()
1186 snprintf(caps->name, sizeof(caps->name), "IDT 82P33 PLL%u", index); in idt82p33_caps_init()
1188 caps->pin_config = pin_cfg; in idt82p33_caps_init()
1193 ppd->index = i; in idt82p33_caps_init()
1194 ppd->func = PTP_PF_NONE; in idt82p33_caps_init()
1195 ppd->chan = index; in idt82p33_caps_init()
1196 snprintf(ppd->name, sizeof(ppd->name), "in%d", 12 + i); in idt82p33_caps_init()
1206 return -EINVAL; in idt82p33_enable_channel()
1208 channel = &idt82p33->channel[index]; in idt82p33_enable_channel()
1212 dev_err(idt82p33->dev, in idt82p33_enable_channel()
1218 idt82p33_caps_init(index, &channel->caps, in idt82p33_enable_channel()
1221 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL); in idt82p33_enable_channel()
1223 if (IS_ERR(channel->ptp_clock)) { in idt82p33_enable_channel()
1224 err = PTR_ERR(channel->ptp_clock); in idt82p33_enable_channel()
1225 channel->ptp_clock = NULL; in idt82p33_enable_channel()
1229 if (!channel->ptp_clock) in idt82p33_enable_channel()
1230 return -ENOTSUPP; in idt82p33_enable_channel()
1234 dev_err(idt82p33->dev, in idt82p33_enable_channel()
1242 dev_err(idt82p33->dev, in idt82p33_enable_channel()
1248 dev_info(idt82p33->dev, "PLL%d registered as ptp%d\n", in idt82p33_enable_channel()
1249 index, channel->ptp_clock->index); in idt82p33_enable_channel()
1264 dev_err(idt82p33->dev, in idt82p33_reset()
1274 dev_err(idt82p33->dev, in idt82p33_reset()
1291 dev_info(idt82p33->dev, "requesting firmware '%s'\n", fname); in idt82p33_load_firmware()
1293 err = request_firmware(&fw, fname, idt82p33->dev); in idt82p33_load_firmware()
1296 dev_err(idt82p33->dev, in idt82p33_load_firmware()
1301 dev_dbg(idt82p33->dev, "firmware size %zu bytes\n", fw->size); in idt82p33_load_firmware()
1303 rec = (struct idt82p33_fwrc *) fw->data; in idt82p33_load_firmware()
1305 for (len = fw->size; len > 0; len -= sizeof(*rec)) { in idt82p33_load_firmware()
1307 if (rec->reserved) { in idt82p33_load_firmware()
1308 dev_err(idt82p33->dev, in idt82p33_load_firmware()
1309 "bad firmware, reserved field non-zero\n"); in idt82p33_load_firmware()
1310 err = -EINVAL; in idt82p33_load_firmware()
1312 val = rec->value; in idt82p33_load_firmware()
1313 loaddr = rec->loaddr; in idt82p33_load_firmware()
1314 page = rec->hiaddr; in idt82p33_load_firmware()
1350 if (idt82p33->extts_mask == 0) in idt82p33_extts_check()
1353 mutex_lock(idt82p33->lock); in idt82p33_extts_check()
1358 if ((idt82p33->extts_mask & mask) == 0) in idt82p33_extts_check()
1365 if (idt82p33->extts_single_shot) { in idt82p33_extts_check()
1366 idt82p33->extts_mask &= ~mask; in idt82p33_extts_check()
1368 /* Re-arm */ in idt82p33_extts_check()
1369 channel = &idt82p33->channel[i]; in idt82p33_extts_check()
1370 arm_tod_read_with_trigger(channel, channel->tod_trigger); in idt82p33_extts_check()
1375 if (idt82p33->extts_mask) in idt82p33_extts_check()
1376 schedule_delayed_work(&idt82p33->extts_work, in idt82p33_extts_check()
1379 mutex_unlock(idt82p33->lock); in idt82p33_extts_check()
1384 struct rsmu_ddata *ddata = dev_get_drvdata(pdev->dev.parent); in idt82p33_probe()
1389 idt82p33 = devm_kzalloc(&pdev->dev, in idt82p33_probe()
1392 return -ENOMEM; in idt82p33_probe()
1394 idt82p33->dev = &pdev->dev; in idt82p33_probe()
1395 idt82p33->mfd = pdev->dev.parent; in idt82p33_probe()
1396 idt82p33->lock = &ddata->lock; in idt82p33_probe()
1397 idt82p33->regmap = ddata->regmap; in idt82p33_probe()
1398 idt82p33->tod_write_overhead_ns = 0; in idt82p33_probe()
1399 idt82p33->calculate_overhead_flag = 0; in idt82p33_probe()
1400 idt82p33->pll_mask = DEFAULT_PLL_MASK; in idt82p33_probe()
1401 idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0; in idt82p33_probe()
1402 idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1; in idt82p33_probe()
1403 idt82p33->extts_mask = 0; in idt82p33_probe()
1404 INIT_DELAYED_WORK(&idt82p33->extts_work, idt82p33_extts_check); in idt82p33_probe()
1406 mutex_lock(idt82p33->lock); in idt82p33_probe()
1413 dev_warn(idt82p33->dev, in idt82p33_probe()
1419 if (idt82p33->pll_mask) { in idt82p33_probe()
1421 if (idt82p33->pll_mask & (1 << i)) in idt82p33_probe()
1426 dev_err(idt82p33->dev, in idt82p33_probe()
1433 dev_err(idt82p33->dev, in idt82p33_probe()
1435 err = -ENODEV; in idt82p33_probe()
1438 mutex_unlock(idt82p33->lock); in idt82p33_probe()
1454 cancel_delayed_work_sync(&idt82p33->extts_work); in idt82p33_remove()
1461 .name = "82p33x1x-phc",