Lines Matching +full:ptp +full:- +full:ref
1 // SPDX-License-Identifier: GPL-2.0+
3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
27 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
33 * over-rides any automatic selection
49 return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count); in idtcm_read()
58 return regmap_bulk_write(idtcm->regmap, module + regaddr, buf, count); in idtcm_write()
64 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data; in contains_full_configuration()
65 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH); in contains_full_configuration()
73 full_count = (scratch - GPIO_USER_CONTROL) - in contains_full_configuration()
74 ((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4; in contains_full_configuration()
82 for (len = fw->size; len > 0; len -= sizeof(*rec)) { in contains_full_configuration()
83 regaddr = rec->hiaddr << 8; in contains_full_configuration()
84 regaddr |= rec->loaddr; in contains_full_configuration()
86 loaddr = rec->loaddr; in contains_full_configuration()
90 /* Top (status registers) and bottom are read-only */ in contains_full_configuration()
115 /* Sub-nanoseconds are in buf[0]. */ in char_array_to_timespec()
119 nsec |= buf[3 - i]; in char_array_to_timespec()
125 sec |= buf[9 - i]; in char_array_to_timespec()
128 ts->tv_sec = sec; in char_array_to_timespec()
129 ts->tv_nsec = nsec; in char_array_to_timespec()
145 nsec = ts->tv_nsec; in timespec_to_char_array()
146 sec = ts->tv_sec; in timespec_to_char_array()
148 /* Sub-nanoseconds are in buf[0]. */ in timespec_to_char_array()
171 return -1; in idtcm_strverscmp()
174 return -1; in idtcm_strverscmp()
180 return -1; in idtcm_strverscmp()
233 i--; in wait_for_boot_status_ready()
237 dev_warn(idtcm->dev, "%s timed out", __func__); in wait_for_boot_status_ready()
239 return -EBUSY; in wait_for_boot_status_ready()
242 static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref) in arm_tod_read_trig_sel_refclk() argument
244 struct idtcm *idtcm = channel->idtcm; in arm_tod_read_trig_sel_refclk()
245 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD); in arm_tod_read_trig_sel_refclk()
250 val |= (ref << WR_REF_INDEX_SHIFT); in arm_tod_read_trig_sel_refclk()
252 err = idtcm_write(idtcm, channel->tod_read_secondary, in arm_tod_read_trig_sel_refclk()
259 err = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd, in arm_tod_read_trig_sel_refclk()
262 dev_err(idtcm->dev, "%s: err = %d", __func__, err); in arm_tod_read_trig_sel_refclk()
276 u8 index = rq->extts.index; in idtcm_extts_enable()
281 int ref; in idtcm_extts_enable() local
283 idtcm = channel->idtcm; in idtcm_extts_enable()
284 old_mask = idtcm->extts_mask; in idtcm_extts_enable()
287 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | in idtcm_extts_enable()
291 return -EOPNOTSUPP; in idtcm_extts_enable()
294 if ((rq->extts.flags & PTP_ENABLE_FEATURE) && in idtcm_extts_enable()
295 (rq->extts.flags & PTP_FALLING_EDGE)) in idtcm_extts_enable()
296 return -EOPNOTSUPP; in idtcm_extts_enable()
299 return -EINVAL; in idtcm_extts_enable()
304 ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->tod); in idtcm_extts_enable()
306 if (ref < 0) { in idtcm_extts_enable()
307 dev_err(idtcm->dev, "%s: No valid pin found for TOD%d!\n", in idtcm_extts_enable()
308 __func__, channel->tod); in idtcm_extts_enable()
309 return -EBUSY; in idtcm_extts_enable()
312 err = arm_tod_read_trig_sel_refclk(&idtcm->channel[index], ref); in idtcm_extts_enable()
315 idtcm->extts_mask |= mask; in idtcm_extts_enable()
316 idtcm->event_channel[index] = channel; in idtcm_extts_enable()
317 idtcm->channel[index].refn = ref; in idtcm_extts_enable()
318 idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask); in idtcm_extts_enable()
323 schedule_delayed_work(&idtcm->extts_work, in idtcm_extts_enable()
327 idtcm->extts_mask &= ~mask; in idtcm_extts_enable()
328 idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask); in idtcm_extts_enable()
330 if (idtcm->extts_mask == 0) in idtcm_extts_enable()
331 cancel_delayed_work(&idtcm->extts_work); in idtcm_extts_enable()
373 dev_warn(idtcm->dev, in wait_for_sys_apll_dpll_lock()
375 return -EPERM; in wait_for_sys_apll_dpll_lock()
381 dev_warn(idtcm->dev, in wait_for_sys_apll_dpll_lock()
385 return -ETIME; in wait_for_sys_apll_dpll_lock()
391 dev_warn(idtcm->dev, "BOOT_STATUS != 0xA0"); in wait_for_chip_ready()
394 dev_warn(idtcm->dev, in wait_for_chip_ready()
401 struct idtcm *idtcm = channel->idtcm; in _idtcm_gettime_triggered()
402 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD); in _idtcm_gettime_triggered()
407 err = idtcm_read(idtcm, channel->tod_read_secondary, in _idtcm_gettime_triggered()
413 return -EBUSY; in _idtcm_gettime_triggered()
415 err = idtcm_read(idtcm, channel->tod_read_secondary, in _idtcm_gettime_triggered()
426 struct idtcm *idtcm = channel->idtcm; in _idtcm_gettime()
427 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD); in _idtcm_gettime()
434 if (timeout-- == 0) in _idtcm_gettime()
435 return -EIO; in _idtcm_gettime()
437 if (idtcm->calculate_overhead_flag) in _idtcm_gettime()
438 idtcm->start_time = ktime_get_raw(); in _idtcm_gettime()
440 err = idtcm_read(idtcm, channel->tod_read_primary, in _idtcm_gettime()
447 err = idtcm_read(idtcm, channel->tod_read_primary, in _idtcm_gettime()
465 extts_channel = &idtcm->channel[todn]; in idtcm_extts_check_channel()
466 ptp_channel = idtcm->event_channel[todn]; in idtcm_extts_check_channel()
469 dco_delay = ptp_channel->dco_delay; in idtcm_extts_check_channel()
475 /* Triggered - save timestamp */ in idtcm_extts_check_channel()
478 event.timestamp = timespec64_to_ns(&ts) - dco_delay; in idtcm_extts_check_channel()
479 ptp_clock_event(ptp_channel->ptp_clock, &event); in idtcm_extts_check_channel()
487 struct idtcm *idtcm = channel->idtcm; in _idtcm_gettime_immediate()
489 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD); in _idtcm_gettime_immediate()
493 err = idtcm_write(idtcm, channel->tod_read_primary, in _idtcm_gettime_immediate()
550 return -EINVAL; in _sync_pll_output()
630 struct idtcm *idtcm = channel->idtcm; in idtcm_sync_pps_output()
638 u16 output_mask = channel->output_mask; in idtcm_sync_pps_output()
695 err = _sync_pll_output(idtcm, pll, channel->sync_src, in idtcm_sync_pps_output()
709 struct idtcm *idtcm = channel->idtcm; in _idtcm_set_dpll_hw_tod()
717 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, in _idtcm_set_dpll_hw_tod()
725 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, in _idtcm_set_dpll_hw_tod()
735 err = idtcm_write(idtcm, channel->hw_dpll_n, in _idtcm_set_dpll_hw_tod()
744 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1, in _idtcm_set_dpll_hw_tod()
748 if (idtcm->calculate_overhead_flag) { in _idtcm_set_dpll_hw_tod()
751 idtcm->start_time); in _idtcm_set_dpll_hw_tod()
753 + idtcm->tod_write_overhead_ns in _idtcm_set_dpll_hw_tod()
758 idtcm->calculate_overhead_flag = 0; in _idtcm_set_dpll_hw_tod()
765 err = idtcm_write(idtcm, channel->hw_dpll_n, in _idtcm_set_dpll_hw_tod()
777 struct idtcm *idtcm = channel->idtcm; in _idtcm_set_dpll_scsr_tod()
788 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE, in _idtcm_set_dpll_scsr_tod()
794 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD, in _idtcm_set_dpll_scsr_tod()
804 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD, in _idtcm_set_dpll_scsr_tod()
815 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD, in _idtcm_set_dpll_scsr_tod()
824 dev_err(idtcm->dev, in _idtcm_set_dpll_scsr_tod()
826 return -EIO; in _idtcm_set_dpll_scsr_tod()
875 base = -EINVAL; in get_output_base_addr()
884 struct idtcm *idtcm = channel->idtcm; in _idtcm_settime_deprecated()
889 dev_err(idtcm->dev, in _idtcm_settime_deprecated()
911 struct idtcm *idtcm = channel->idtcm; in idtcm_set_phase_pull_in_offset()
919 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET, in idtcm_set_phase_pull_in_offset()
930 struct idtcm *idtcm = channel->idtcm; in idtcm_set_phase_pull_in_slope_limit()
941 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, in idtcm_set_phase_pull_in_slope_limit()
950 struct idtcm *idtcm = channel->idtcm; in idtcm_start_phase_pull_in()
953 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL, in idtcm_start_phase_pull_in()
960 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, in idtcm_start_phase_pull_in()
963 err = -EBUSY; in idtcm_start_phase_pull_in()
975 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns); in do_phase_pull_in_fw()
990 struct idtcm *idtcm = channel->idtcm; in set_tod_write_overhead()
1002 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0, in set_tod_write_overhead()
1008 err = idtcm_write(idtcm, channel->hw_dpll_n, in set_tod_write_overhead()
1027 idtcm->tod_write_overhead_ns = lowest_ns; in set_tod_write_overhead()
1035 struct idtcm *idtcm = channel->idtcm; in _idtcm_adjtime_deprecated()
1040 err = channel->do_phase_pull_in(channel, delta, 0); in _idtcm_adjtime_deprecated()
1042 idtcm->calculate_overhead_flag = 1; in _idtcm_adjtime_deprecated()
1073 IDTCM_FW_REG(idtcm->fw_ver, V520, SM_RESET), in idtcm_state_machine_reset()
1082 dev_dbg(idtcm->dev, in idtcm_state_machine_reset()
1089 dev_err(idtcm->dev, in idtcm_state_machine_reset()
1152 SET_U16_LSB(idtcm->channel[0].output_mask, val); in set_pll_output_mask()
1155 SET_U16_MSB(idtcm->channel[0].output_mask, val); in set_pll_output_mask()
1158 SET_U16_LSB(idtcm->channel[1].output_mask, val); in set_pll_output_mask()
1161 SET_U16_MSB(idtcm->channel[1].output_mask, val); in set_pll_output_mask()
1164 SET_U16_LSB(idtcm->channel[2].output_mask, val); in set_pll_output_mask()
1167 SET_U16_MSB(idtcm->channel[2].output_mask, val); in set_pll_output_mask()
1170 SET_U16_LSB(idtcm->channel[3].output_mask, val); in set_pll_output_mask()
1173 SET_U16_MSB(idtcm->channel[3].output_mask, val); in set_pll_output_mask()
1176 err = -EFAULT; /* Bad address */; in set_pll_output_mask()
1186 dev_err(idtcm->dev, "ToD%d not supported", index); in set_tod_ptp_pll()
1187 return -EINVAL; in set_tod_ptp_pll()
1191 dev_err(idtcm->dev, "Pll%d not supported", pll); in set_tod_ptp_pll()
1192 return -EINVAL; in set_tod_ptp_pll()
1195 idtcm->channel[index].pll = pll; in set_tod_ptp_pll()
1209 dev_err(idtcm->dev, "Invalid TOD mask 0x%02x", val); in check_and_set_masks()
1210 err = -EINVAL; in check_and_set_masks()
1212 idtcm->tod_mask = val; in check_and_set_masks()
1240 dev_dbg(idtcm->dev, "tod_mask = 0x%02x", idtcm->tod_mask); in display_pll_and_masks()
1245 if (mask & idtcm->tod_mask) in display_pll_and_masks()
1246 dev_dbg(idtcm->dev, in display_pll_and_masks()
1248 i, idtcm->channel[i].pll, in display_pll_and_masks()
1249 idtcm->channel[i].output_mask); in display_pll_and_masks()
1256 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH); in idtcm_load_firmware()
1269 dev_info(idtcm->dev, "requesting firmware '%s'", fname); in idtcm_load_firmware()
1273 dev_err(idtcm->dev, in idtcm_load_firmware()
1278 dev_dbg(idtcm->dev, "firmware size %zu bytes", fw->size); in idtcm_load_firmware()
1280 rec = (struct idtcm_fwrc *) fw->data; in idtcm_load_firmware()
1285 for (len = fw->size; len > 0; len -= sizeof(*rec)) { in idtcm_load_firmware()
1286 if (rec->reserved) { in idtcm_load_firmware()
1287 dev_err(idtcm->dev, in idtcm_load_firmware()
1288 "bad firmware, reserved field non-zero"); in idtcm_load_firmware()
1289 err = -EINVAL; in idtcm_load_firmware()
1291 regaddr = rec->hiaddr << 8; in idtcm_load_firmware()
1292 regaddr |= rec->loaddr; in idtcm_load_firmware()
1294 val = rec->value; in idtcm_load_firmware()
1295 loaddr = rec->loaddr; in idtcm_load_firmware()
1302 if (err != -EINVAL) { in idtcm_load_firmware()
1305 /* Top (status registers) and bottom are read-only */ in idtcm_load_firmware()
1330 struct idtcm *idtcm = channel->idtcm; in idtcm_output_enable()
1335 base = get_output_base_addr(idtcm->fw_ver, outn); in idtcm_output_enable()
1338 dev_err(idtcm->dev, in idtcm_output_enable()
1339 "%s - Unsupported out%d", __func__, outn); in idtcm_output_enable()
1359 struct idtcm *idtcm = channel->idtcm; in idtcm_perout_enable()
1363 err = idtcm_output_enable(channel, enable, perout->index); in idtcm_perout_enable()
1366 dev_err(idtcm->dev, "Unable to set output enable"); in idtcm_perout_enable()
1377 struct idtcm *idtcm = channel->idtcm; in idtcm_get_pll_mode()
1381 err = idtcm_read(idtcm, channel->dpll_n, in idtcm_get_pll_mode()
1382 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE), in idtcm_get_pll_mode()
1395 struct idtcm *idtcm = channel->idtcm; in idtcm_set_pll_mode()
1399 err = idtcm_read(idtcm, channel->dpll_n, in idtcm_set_pll_mode()
1400 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE), in idtcm_set_pll_mode()
1409 err = idtcm_write(idtcm, channel->dpll_n, in idtcm_set_pll_mode()
1410 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE), in idtcm_set_pll_mode()
1416 enum manual_reference *ref) in idtcm_get_manual_reference() argument
1418 struct idtcm *idtcm = channel->idtcm; in idtcm_get_manual_reference()
1422 err = idtcm_read(idtcm, channel->dpll_ctrl_n, in idtcm_get_manual_reference()
1430 *ref = dpll_manu_ref_cfg >> MANUAL_REFERENCE_SHIFT; in idtcm_get_manual_reference()
1436 enum manual_reference ref) in idtcm_set_manual_reference() argument
1438 struct idtcm *idtcm = channel->idtcm; in idtcm_set_manual_reference()
1442 err = idtcm_read(idtcm, channel->dpll_ctrl_n, in idtcm_set_manual_reference()
1450 dpll_manu_ref_cfg |= (ref << MANUAL_REFERENCE_SHIFT); in idtcm_set_manual_reference()
1452 err = idtcm_write(idtcm, channel->dpll_ctrl_n, in idtcm_set_manual_reference()
1461 struct idtcm *idtcm = channel->idtcm; in configure_dpll_mode_write_frequency()
1467 dev_err(idtcm->dev, "Failed to set pll mode to write frequency"); in configure_dpll_mode_write_frequency()
1469 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY; in configure_dpll_mode_write_frequency()
1476 struct idtcm *idtcm = channel->idtcm; in configure_dpll_mode_write_phase()
1482 dev_err(idtcm->dev, "Failed to set pll mode to write phase"); in configure_dpll_mode_write_phase()
1484 channel->mode = PTP_PLL_MODE_WRITE_PHASE; in configure_dpll_mode_write_phase()
1491 struct idtcm *idtcm = channel->idtcm; in configure_manual_reference_write_frequency()
1497 dev_err(idtcm->dev, "Failed to set manual reference to write frequency"); in configure_manual_reference_write_frequency()
1499 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY; in configure_manual_reference_write_frequency()
1506 struct idtcm *idtcm = channel->idtcm; in configure_manual_reference_write_phase()
1512 dev_err(idtcm->dev, "Failed to set manual reference to write phase"); in configure_manual_reference_write_phase()
1514 channel->mode = PTP_PLL_MODE_WRITE_PHASE; in configure_manual_reference_write_phase()
1523 err = _idtcm_adjfine(channel, channel->current_freq_scaled_ppm); in idtcm_stop_phase_pull_in()
1527 channel->phase_pull_in = false; in idtcm_stop_phase_pull_in()
1532 static long idtcm_work_handler(struct ptp_clock_info *ptp) in idtcm_work_handler() argument
1534 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); in idtcm_work_handler()
1535 struct idtcm *idtcm = channel->idtcm; in idtcm_work_handler()
1537 mutex_lock(idtcm->lock); in idtcm_work_handler()
1541 mutex_unlock(idtcm->lock); in idtcm_work_handler()
1544 return -1; in idtcm_work_handler()
1559 else if (current_ppm < -max_scaled_ppm) in phase_pull_in_scaled_ppm()
1560 current_ppm = -max_scaled_ppm; in phase_pull_in_scaled_ppm()
1569 s32 current_ppm = channel->current_freq_scaled_ppm; in do_phase_pull_in_sw()
1585 /* For most cases, keep phase pull-in duration 1 second */ in do_phase_pull_in_sw()
1599 /* schedule the worker to cancel phase pull-in */ in do_phase_pull_in_sw()
1600 ptp_schedule_worker(channel->ptp_clock, in do_phase_pull_in_sw()
1601 msecs_to_jiffies(duration_ms) - 1); in do_phase_pull_in_sw()
1603 channel->phase_pull_in = true; in do_phase_pull_in_sw()
1609 enum manual_reference ref) in initialize_operating_mode_with_manual_reference() argument
1611 struct idtcm *idtcm = channel->idtcm; in initialize_operating_mode_with_manual_reference()
1613 channel->mode = PTP_PLL_MODE_UNSUPPORTED; in initialize_operating_mode_with_manual_reference()
1614 channel->configure_write_frequency = configure_manual_reference_write_frequency; in initialize_operating_mode_with_manual_reference()
1615 channel->configure_write_phase = configure_manual_reference_write_phase; in initialize_operating_mode_with_manual_reference()
1616 channel->do_phase_pull_in = do_phase_pull_in_sw; in initialize_operating_mode_with_manual_reference()
1618 switch (ref) { in initialize_operating_mode_with_manual_reference()
1620 channel->mode = PTP_PLL_MODE_WRITE_PHASE; in initialize_operating_mode_with_manual_reference()
1623 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY; in initialize_operating_mode_with_manual_reference()
1626 dev_warn(idtcm->dev, in initialize_operating_mode_with_manual_reference()
1627 "Unsupported MANUAL_REFERENCE: 0x%02x", ref); in initialize_operating_mode_with_manual_reference()
1636 struct idtcm *idtcm = channel->idtcm; in initialize_operating_mode_with_pll_mode()
1639 channel->mode = PTP_PLL_MODE_UNSUPPORTED; in initialize_operating_mode_with_pll_mode()
1640 channel->configure_write_frequency = configure_dpll_mode_write_frequency; in initialize_operating_mode_with_pll_mode()
1641 channel->configure_write_phase = configure_dpll_mode_write_phase; in initialize_operating_mode_with_pll_mode()
1642 channel->do_phase_pull_in = do_phase_pull_in_fw; in initialize_operating_mode_with_pll_mode()
1646 channel->mode = PTP_PLL_MODE_WRITE_PHASE; in initialize_operating_mode_with_pll_mode()
1649 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY; in initialize_operating_mode_with_pll_mode()
1652 dev_err(idtcm->dev, in initialize_operating_mode_with_pll_mode()
1654 err = -EINVAL; in initialize_operating_mode_with_pll_mode()
1662 enum manual_reference ref = MANU_REF_XO_DPLL; in initialize_dco_operating_mode() local
1664 struct idtcm *idtcm = channel->idtcm; in initialize_dco_operating_mode()
1667 channel->mode = PTP_PLL_MODE_UNSUPPORTED; in initialize_dco_operating_mode()
1671 dev_err(idtcm->dev, "Unable to read pll mode!"); in initialize_dco_operating_mode()
1676 err = idtcm_get_manual_reference(channel, &ref); in initialize_dco_operating_mode()
1678 dev_err(idtcm->dev, "Unable to read manual reference!"); in initialize_dco_operating_mode()
1681 err = initialize_operating_mode_with_manual_reference(channel, ref); in initialize_dco_operating_mode()
1686 if (channel->mode == PTP_PLL_MODE_WRITE_PHASE) in initialize_dco_operating_mode()
1687 channel->configure_write_frequency(channel); in initialize_dco_operating_mode()
1692 /* PTP Hardware Clock interface */
1697 * Destination signed register is 32-bit register in resolution of 50ps
1702 static s32 idtcm_getmaxphase(struct ptp_clock_info *ptp __always_unused) in idtcm_getmaxphase()
1715 struct idtcm *idtcm = channel->idtcm; in _idtcm_adjphase()
1721 if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) { in _idtcm_adjphase()
1722 err = channel->configure_write_phase(channel); in _idtcm_adjphase()
1734 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE, in _idtcm_adjphase()
1742 struct idtcm *idtcm = channel->idtcm; in _idtcm_adjfine()
1748 if (channel->mode != PTP_PLL_MODE_WRITE_FREQUENCY) { in _idtcm_adjfine()
1749 err = channel->configure_write_frequency(channel); in _idtcm_adjfine()
1755 * Frequency Control Word unit is: 1.11 * 10^-10 ppm in _idtcm_adjfine()
1759 * FCW = ---------- in _idtcm_adjfine()
1764 * FCW = ------------- in _idtcm_adjfine()
1768 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */ in _idtcm_adjfine()
1778 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ, in _idtcm_adjfine()
1784 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) in idtcm_gettime() argument
1786 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); in idtcm_gettime()
1787 struct idtcm *idtcm = channel->idtcm; in idtcm_gettime()
1790 mutex_lock(idtcm->lock); in idtcm_gettime()
1792 mutex_unlock(idtcm->lock); in idtcm_gettime()
1795 dev_err(idtcm->dev, "Failed at line %d in %s!", in idtcm_gettime()
1801 static int idtcm_settime_deprecated(struct ptp_clock_info *ptp, in idtcm_settime_deprecated() argument
1804 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); in idtcm_settime_deprecated()
1805 struct idtcm *idtcm = channel->idtcm; in idtcm_settime_deprecated()
1808 mutex_lock(idtcm->lock); in idtcm_settime_deprecated()
1810 mutex_unlock(idtcm->lock); in idtcm_settime_deprecated()
1813 dev_err(idtcm->dev, in idtcm_settime_deprecated()
1819 static int idtcm_settime(struct ptp_clock_info *ptp, in idtcm_settime() argument
1822 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); in idtcm_settime()
1823 struct idtcm *idtcm = channel->idtcm; in idtcm_settime()
1826 mutex_lock(idtcm->lock); in idtcm_settime()
1828 mutex_unlock(idtcm->lock); in idtcm_settime()
1831 dev_err(idtcm->dev, in idtcm_settime()
1837 static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta) in idtcm_adjtime_deprecated() argument
1839 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); in idtcm_adjtime_deprecated()
1840 struct idtcm *idtcm = channel->idtcm; in idtcm_adjtime_deprecated()
1843 mutex_lock(idtcm->lock); in idtcm_adjtime_deprecated()
1845 mutex_unlock(idtcm->lock); in idtcm_adjtime_deprecated()
1848 dev_err(idtcm->dev, in idtcm_adjtime_deprecated()
1854 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) in idtcm_adjtime() argument
1856 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); in idtcm_adjtime()
1857 struct idtcm *idtcm = channel->idtcm; in idtcm_adjtime()
1862 if (channel->phase_pull_in == true) in idtcm_adjtime()
1863 return -EBUSY; in idtcm_adjtime()
1865 mutex_lock(idtcm->lock); in idtcm_adjtime()
1868 err = channel->do_phase_pull_in(channel, delta, 0); in idtcm_adjtime()
1874 ts = ns_to_timespec64(-delta); in idtcm_adjtime()
1880 mutex_unlock(idtcm->lock); in idtcm_adjtime()
1883 dev_err(idtcm->dev, in idtcm_adjtime()
1889 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta) in idtcm_adjphase() argument
1891 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); in idtcm_adjphase()
1892 struct idtcm *idtcm = channel->idtcm; in idtcm_adjphase()
1895 mutex_lock(idtcm->lock); in idtcm_adjphase()
1897 mutex_unlock(idtcm->lock); in idtcm_adjphase()
1900 dev_err(idtcm->dev, in idtcm_adjphase()
1906 static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) in idtcm_adjfine() argument
1908 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); in idtcm_adjfine()
1909 struct idtcm *idtcm = channel->idtcm; in idtcm_adjfine()
1912 if (channel->phase_pull_in == true) in idtcm_adjfine()
1915 if (scaled_ppm == channel->current_freq_scaled_ppm) in idtcm_adjfine()
1918 mutex_lock(idtcm->lock); in idtcm_adjfine()
1920 mutex_unlock(idtcm->lock); in idtcm_adjfine()
1923 dev_err(idtcm->dev, in idtcm_adjfine()
1926 channel->current_freq_scaled_ppm = scaled_ppm; in idtcm_adjfine()
1931 static int idtcm_enable(struct ptp_clock_info *ptp, in idtcm_enable() argument
1934 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps); in idtcm_enable()
1935 struct idtcm *idtcm = channel->idtcm; in idtcm_enable()
1936 int err = -EOPNOTSUPP; in idtcm_enable()
1938 mutex_lock(idtcm->lock); in idtcm_enable()
1940 switch (rq->type) { in idtcm_enable()
1943 err = idtcm_perout_enable(channel, &rq->perout, false); in idtcm_enable()
1944 /* Only accept a 1-PPS aligned to the second. */ in idtcm_enable()
1945 else if (rq->perout.start.nsec || rq->perout.period.sec != 1 || in idtcm_enable()
1946 rq->perout.period.nsec) in idtcm_enable()
1947 err = -ERANGE; in idtcm_enable()
1949 err = idtcm_perout_enable(channel, &rq->perout, true); in idtcm_enable()
1958 mutex_unlock(idtcm->lock); in idtcm_enable()
1961 dev_err(channel->idtcm->dev, in idtcm_enable()
1969 struct idtcm *idtcm = channel->idtcm; in idtcm_enable_tod()
1971 u16 tod_cfg = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_CFG); in idtcm_enable_tod()
1978 err = idtcm_read(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg)); in idtcm_enable_tod()
1984 err = idtcm_write(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg)); in idtcm_enable_tod()
1988 if (idtcm->fw_ver < V487) in idtcm_enable_tod()
2013 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u", in idtcm_set_version_info()
2016 idtcm->fw_ver = idtcm_fw_version(idtcm->version); in idtcm_set_version_info()
2018 dev_info(idtcm->dev, in idtcm_set_version_info()
2024 static int idtcm_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, in idtcm_verify_pin() argument
2033 return -1; in idtcm_verify_pin()
2076 struct idtcm *idtcm = channel->idtcm; in configure_channel_pll()
2079 switch (channel->pll) { in configure_channel_pll()
2081 channel->dpll_freq = DPLL_FREQ_0; in configure_channel_pll()
2082 channel->dpll_n = DPLL_0; in configure_channel_pll()
2083 channel->hw_dpll_n = HW_DPLL_0; in configure_channel_pll()
2084 channel->dpll_phase = DPLL_PHASE_0; in configure_channel_pll()
2085 channel->dpll_ctrl_n = DPLL_CTRL_0; in configure_channel_pll()
2086 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0; in configure_channel_pll()
2089 channel->dpll_freq = DPLL_FREQ_1; in configure_channel_pll()
2090 channel->dpll_n = DPLL_1; in configure_channel_pll()
2091 channel->hw_dpll_n = HW_DPLL_1; in configure_channel_pll()
2092 channel->dpll_phase = DPLL_PHASE_1; in configure_channel_pll()
2093 channel->dpll_ctrl_n = DPLL_CTRL_1; in configure_channel_pll()
2094 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1; in configure_channel_pll()
2097 channel->dpll_freq = DPLL_FREQ_2; in configure_channel_pll()
2098 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_2); in configure_channel_pll()
2099 channel->hw_dpll_n = HW_DPLL_2; in configure_channel_pll()
2100 channel->dpll_phase = DPLL_PHASE_2; in configure_channel_pll()
2101 channel->dpll_ctrl_n = DPLL_CTRL_2; in configure_channel_pll()
2102 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2; in configure_channel_pll()
2105 channel->dpll_freq = DPLL_FREQ_3; in configure_channel_pll()
2106 channel->dpll_n = DPLL_3; in configure_channel_pll()
2107 channel->hw_dpll_n = HW_DPLL_3; in configure_channel_pll()
2108 channel->dpll_phase = DPLL_PHASE_3; in configure_channel_pll()
2109 channel->dpll_ctrl_n = DPLL_CTRL_3; in configure_channel_pll()
2110 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3; in configure_channel_pll()
2113 channel->dpll_freq = DPLL_FREQ_4; in configure_channel_pll()
2114 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_4); in configure_channel_pll()
2115 channel->hw_dpll_n = HW_DPLL_4; in configure_channel_pll()
2116 channel->dpll_phase = DPLL_PHASE_4; in configure_channel_pll()
2117 channel->dpll_ctrl_n = DPLL_CTRL_4; in configure_channel_pll()
2118 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4; in configure_channel_pll()
2121 channel->dpll_freq = DPLL_FREQ_5; in configure_channel_pll()
2122 channel->dpll_n = DPLL_5; in configure_channel_pll()
2123 channel->hw_dpll_n = HW_DPLL_5; in configure_channel_pll()
2124 channel->dpll_phase = DPLL_PHASE_5; in configure_channel_pll()
2125 channel->dpll_ctrl_n = DPLL_CTRL_5; in configure_channel_pll()
2126 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5; in configure_channel_pll()
2129 channel->dpll_freq = DPLL_FREQ_6; in configure_channel_pll()
2130 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_6); in configure_channel_pll()
2131 channel->hw_dpll_n = HW_DPLL_6; in configure_channel_pll()
2132 channel->dpll_phase = DPLL_PHASE_6; in configure_channel_pll()
2133 channel->dpll_ctrl_n = DPLL_CTRL_6; in configure_channel_pll()
2134 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6; in configure_channel_pll()
2137 channel->dpll_freq = DPLL_FREQ_7; in configure_channel_pll()
2138 channel->dpll_n = DPLL_7; in configure_channel_pll()
2139 channel->hw_dpll_n = HW_DPLL_7; in configure_channel_pll()
2140 channel->dpll_phase = DPLL_PHASE_7; in configure_channel_pll()
2141 channel->dpll_ctrl_n = DPLL_CTRL_7; in configure_channel_pll()
2142 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7; in configure_channel_pll()
2145 err = -EINVAL; in configure_channel_pll()
2152 * Compensate for the PTP DCO input-to-output delay.
2157 struct idtcm *idtcm = channel->idtcm; in idtcm_get_dco_delay()
2165 err = idtcm_read(idtcm, channel->dpll_ctrl_n, in idtcm_get_dco_delay()
2170 err = idtcm_read(idtcm, channel->dpll_ctrl_n, in idtcm_get_dco_delay()
2191 enum fw_version fw_ver = channel->idtcm->fw_ver; in configure_channel_tod()
2196 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_0); in configure_channel_tod()
2197 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_0); in configure_channel_tod()
2198 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_0); in configure_channel_tod()
2199 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_0); in configure_channel_tod()
2200 channel->sync_src = SYNC_SOURCE_DPLL0_TOD_PPS; in configure_channel_tod()
2203 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_1); in configure_channel_tod()
2204 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_1); in configure_channel_tod()
2205 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_1); in configure_channel_tod()
2206 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_1); in configure_channel_tod()
2207 channel->sync_src = SYNC_SOURCE_DPLL1_TOD_PPS; in configure_channel_tod()
2210 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_2); in configure_channel_tod()
2211 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_2); in configure_channel_tod()
2212 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_2); in configure_channel_tod()
2213 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_2); in configure_channel_tod()
2214 channel->sync_src = SYNC_SOURCE_DPLL2_TOD_PPS; in configure_channel_tod()
2217 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_3); in configure_channel_tod()
2218 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_3); in configure_channel_tod()
2219 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_3); in configure_channel_tod()
2220 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_3); in configure_channel_tod()
2221 channel->sync_src = SYNC_SOURCE_DPLL3_TOD_PPS; in configure_channel_tod()
2224 return -EINVAL; in configure_channel_tod()
2237 return -EINVAL; in idtcm_enable_channel()
2239 channel = &idtcm->channel[index]; in idtcm_enable_channel()
2241 channel->idtcm = idtcm; in idtcm_enable_channel()
2242 channel->current_freq_scaled_ppm = 0; in idtcm_enable_channel()
2254 if (idtcm->fw_ver < V487) in idtcm_enable_channel()
2255 channel->caps = idtcm_caps_deprecated; in idtcm_enable_channel()
2257 channel->caps = idtcm_caps; in idtcm_enable_channel()
2259 snprintf(channel->caps.name, sizeof(channel->caps.name), in idtcm_enable_channel()
2262 channel->caps.pin_config = pin_config[index]; in idtcm_enable_channel()
2264 for (i = 0; i < channel->caps.n_pins; ++i) { in idtcm_enable_channel()
2265 struct ptp_pin_desc *ppd = &channel->caps.pin_config[i]; in idtcm_enable_channel()
2267 snprintf(ppd->name, sizeof(ppd->name), "input_ref%d", i); in idtcm_enable_channel()
2268 ppd->index = i; in idtcm_enable_channel()
2269 ppd->func = PTP_PF_NONE; in idtcm_enable_channel()
2270 ppd->chan = index; in idtcm_enable_channel()
2279 dev_err(idtcm->dev, in idtcm_enable_channel()
2284 channel->dco_delay = idtcm_get_dco_delay(channel); in idtcm_enable_channel()
2286 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL); in idtcm_enable_channel()
2288 if (IS_ERR(channel->ptp_clock)) { in idtcm_enable_channel()
2289 err = PTR_ERR(channel->ptp_clock); in idtcm_enable_channel()
2290 channel->ptp_clock = NULL; in idtcm_enable_channel()
2294 if (!channel->ptp_clock) in idtcm_enable_channel()
2295 return -ENOTSUPP; in idtcm_enable_channel()
2297 dev_info(idtcm->dev, "PLL%d registered as ptp%d", in idtcm_enable_channel()
2298 index, channel->ptp_clock->index); in idtcm_enable_channel()
2309 return -EINVAL; in idtcm_enable_extts_channel()
2311 channel = &idtcm->channel[index]; in idtcm_enable_extts_channel()
2312 channel->idtcm = idtcm; in idtcm_enable_extts_channel()
2319 channel->idtcm = idtcm; in idtcm_enable_extts_channel()
2332 if (idtcm->extts_mask == 0) in idtcm_extts_check()
2335 mutex_lock(idtcm->lock); in idtcm_extts_check()
2340 if ((idtcm->extts_mask & mask) == 0) in idtcm_extts_check()
2347 if (idtcm->extts_single_shot) { in idtcm_extts_check()
2348 idtcm->extts_mask &= ~mask; in idtcm_extts_check()
2350 /* Re-arm */ in idtcm_extts_check()
2351 channel = &idtcm->channel[i]; in idtcm_extts_check()
2352 arm_tod_read_trig_sel_refclk(channel, channel->refn); in idtcm_extts_check()
2357 if (idtcm->extts_mask) in idtcm_extts_check()
2358 schedule_delayed_work(&idtcm->extts_work, in idtcm_extts_check()
2361 mutex_unlock(idtcm->lock); in idtcm_extts_check()
2370 channel = &idtcm->channel[i]; in ptp_clock_unregister_all()
2371 if (channel->ptp_clock) in ptp_clock_unregister_all()
2372 ptp_clock_unregister(channel->ptp_clock); in ptp_clock_unregister_all()
2378 idtcm->tod_mask = DEFAULT_TOD_MASK; in set_default_masks()
2379 idtcm->extts_mask = 0; in set_default_masks()
2381 idtcm->channel[0].tod = 0; in set_default_masks()
2382 idtcm->channel[1].tod = 1; in set_default_masks()
2383 idtcm->channel[2].tod = 2; in set_default_masks()
2384 idtcm->channel[3].tod = 3; in set_default_masks()
2386 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL; in set_default_masks()
2387 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL; in set_default_masks()
2388 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL; in set_default_masks()
2389 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL; in set_default_masks()
2391 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0; in set_default_masks()
2392 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1; in set_default_masks()
2393 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2; in set_default_masks()
2394 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3; in set_default_masks()
2399 struct rsmu_ddata *ddata = dev_get_drvdata(pdev->dev.parent); in idtcm_probe()
2404 idtcm = devm_kzalloc(&pdev->dev, sizeof(struct idtcm), GFP_KERNEL); in idtcm_probe()
2407 return -ENOMEM; in idtcm_probe()
2409 idtcm->dev = &pdev->dev; in idtcm_probe()
2410 idtcm->mfd = pdev->dev.parent; in idtcm_probe()
2411 idtcm->lock = &ddata->lock; in idtcm_probe()
2412 idtcm->regmap = ddata->regmap; in idtcm_probe()
2413 idtcm->calculate_overhead_flag = 0; in idtcm_probe()
2415 INIT_DELAYED_WORK(&idtcm->extts_work, idtcm_extts_check); in idtcm_probe()
2419 mutex_lock(idtcm->lock); in idtcm_probe()
2423 err = idtcm_load_firmware(idtcm, &pdev->dev); in idtcm_probe()
2426 dev_warn(idtcm->dev, "loading firmware failed with %d", err); in idtcm_probe()
2430 if (idtcm->tod_mask) { in idtcm_probe()
2432 if (idtcm->tod_mask & (1 << i)) in idtcm_probe()
2437 dev_err(idtcm->dev, in idtcm_probe()
2443 dev_err(idtcm->dev, in idtcm_probe()
2445 err = -ENODEV; in idtcm_probe()
2448 mutex_unlock(idtcm->lock); in idtcm_probe()
2464 idtcm->extts_mask = 0; in idtcm_remove()
2466 cancel_delayed_work_sync(&idtcm->extts_work); in idtcm_remove()
2471 .name = "8a3400x-phc",