6  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
20 #include <linux/reset-controller.h>
26 #include <dt-bindings/reset/sama7g5-reset.h>
37 #define AT91_RSTC_NRSTL		BIT(16)		/* NRST Pin Level */
47  * enum reset_type - reset types
48  * @RESET_TYPE_GENERAL:		first power-up reset
69  * struct at91_reset - AT91 reset specific data structure
97  * struct at91_reset_data - AT91 reset data
112 * reset register it can be left driving the data bus and
140 		: "r" (reset->ramc_base[0]),  in at91_reset()
141 		  "r" (reset->ramc_base[1]),  in at91_reset()
142 		  "r" (reset->rstc_base),  in at91_reset()
145 		  "r" (reset->data->reset_args),  in at91_reset()
146 		  "r" (reset->ramc_lpr)  in at91_reset()
154 	u32 reg = readl(reset->rstc_base + AT91_RSTC_SR);  in at91_reset_reason()
202 		.compatible = "atmel,at91sam9260-sdramc",
206 		.compatible = "atmel,at91sam9g45-ddramc",
229 		.compatible = "atmel,at91sam9260-rstc",
233 		.compatible = "atmel,at91sam9g45-rstc",
237 		.compatible = "atmel,sama5d3-rstc",
241 		.compatible = "atmel,samx7-rstc",
245 		.compatible = "microchip,sam9x60-rstc",
249 		.compatible = "microchip,sama7g5-rstc",
263 	spin_lock_irqsave(&reset->lock, flags);  in at91_reset_update()
264 	val = readl_relaxed(reset->dev_base);  in at91_reset_update()
269 	writel_relaxed(val, reset->dev_base);  in at91_reset_update()
270 	spin_unlock_irqrestore(&reset->lock, flags);  in at91_reset_update()
293 	val = readl_relaxed(reset->dev_base);  in at91_reset_dev_status()
309 	if (!reset->data->n_device_reset ||  in at91_reset_of_xlate()
310 	    (reset_spec->args[0] < reset->data->device_reset_min_id ||  in at91_reset_of_xlate()
311 	     reset_spec->args[0] > reset->data->device_reset_max_id))  in at91_reset_of_xlate()
312 		return -EINVAL;  in at91_reset_of_xlate()
314 	return reset_spec->args[0];  in at91_reset_of_xlate()
320 	if (!reset->data->n_device_reset)  in at91_rcdev_init()
323 	reset->dev_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 1,  in at91_rcdev_init()
325 	if (IS_ERR(reset->dev_base))  in at91_rcdev_init()
326 		return -ENODEV;  in at91_rcdev_init()
328 	spin_lock_init(&reset->lock);  in at91_rcdev_init()
329 	reset->rcdev.ops = &at91_reset_ops;  in at91_rcdev_init()
330 	reset->rcdev.owner = THIS_MODULE;  in at91_rcdev_init()
331 	reset->rcdev.of_node = pdev->dev.of_node;  in at91_rcdev_init()
332 	reset->rcdev.nr_resets = reset->data->n_device_reset;  in at91_rcdev_init()
333 	reset->rcdev.of_reset_n_cells = 1;  in at91_rcdev_init()
334 	reset->rcdev.of_xlate = at91_reset_of_xlate;  in at91_rcdev_init()
336 	return devm_reset_controller_register(&pdev->dev, &reset->rcdev);  in at91_rcdev_init()
346 	reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);  in at91_reset_probe()
348 		return -ENOMEM;  in at91_reset_probe()
350 	reset->rstc_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);  in at91_reset_probe()
351 	if (IS_ERR(reset->rstc_base)) {  in at91_reset_probe()
352 		dev_err(&pdev->dev, "Could not map reset controller address\n");  in at91_reset_probe()
353 		return -ENODEV;  in at91_reset_probe()
356 	if (!of_device_is_compatible(pdev->dev.of_node, "atmel,sama5d3-rstc")) {  in at91_reset_probe()
359 			reset->ramc_lpr = (u32)match->data;  in at91_reset_probe()
360 			reset->ramc_base[idx] = devm_of_iomap(&pdev->dev, np, 0, NULL);  in at91_reset_probe()
361 			if (IS_ERR(reset->ramc_base[idx])) {  in at91_reset_probe()
362 				dev_err(&pdev->dev, "Could not map ram controller address\n");  in at91_reset_probe()
364 				return -ENODEV;  in at91_reset_probe()
370 	reset->data = device_get_match_data(&pdev->dev);  in at91_reset_probe()
371 	if (!reset->data)  in at91_reset_probe()
372 		return -ENODEV;  in at91_reset_probe()
374 	reset->nb.notifier_call = at91_reset;  in at91_reset_probe()
375 	reset->nb.priority = 192;  in at91_reset_probe()
377 	reset->sclk = devm_clk_get(&pdev->dev, NULL);  in at91_reset_probe()
378 	if (IS_ERR(reset->sclk))  in at91_reset_probe()
379 		return PTR_ERR(reset->sclk);  in at91_reset_probe()
381 	ret = clk_prepare_enable(reset->sclk);  in at91_reset_probe()
383 		dev_err(&pdev->dev, "Could not enable slow clock\n");  in at91_reset_probe()
393 	if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) {  in at91_reset_probe()
394 		u32 val = readl(reset->rstc_base + AT91_RSTC_MR);  in at91_reset_probe()
397 		       reset->rstc_base + AT91_RSTC_MR);  in at91_reset_probe()
400 	ret = register_restart_handler(&reset->nb);  in at91_reset_probe()
404 	ret = device_create_file(&pdev->dev, &dev_attr_power_on_reason);  in at91_reset_probe()
406 		dev_err(&pdev->dev, "Could not create sysfs entry\n");  in at91_reset_probe()
410 	dev_info(&pdev->dev, "Starting after %s\n", at91_reset_reason(reset));  in at91_reset_probe()
415 	clk_disable_unprepare(reset->sclk);  in at91_reset_probe()
423 	unregister_restart_handler(&reset->nb);  in at91_reset_remove()
424 	clk_disable_unprepare(reset->sclk);  in at91_reset_remove()
431 		.name = "at91-reset",