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1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Tero Kristo <t-kristo@ti.com>
19 #include <linux/reset-controller.h>
24 #include <linux/platform_data/ti-prm.h>
35 unsigned long statechange:1; /* Optional low-power state change */
89 #define OMAP_PRM_HAS_RSTCTRL BIT(0)
141 { .rst = 0, .st = 0 },
142 { .rst = -1 },
146 { .rst = 0, .st = 0 },
148 { .rst = -1 },
152 { .rst = 0, .st = 0 },
155 { .rst = -1 },
160 .name = "mpu", .base = 0x4a306300,
161 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
164 .name = "tesla", .base = 0x4a306400,
165 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
166 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
169 .name = "abe", .base = 0x4a306500,
170 .pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_all,
173 .name = "always_on_core", .base = 0x4a306600,
174 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
177 .name = "core", .base = 0x4a306700,
178 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
179 .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati",
184 .name = "ivahd", .base = 0x4a306f00,
185 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
186 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012
189 .name = "cam", .base = 0x4a307000,
190 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
193 .name = "dss", .base = 0x4a307100,
194 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact
197 .name = "gfx", .base = 0x4a307200,
198 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
201 .name = "l3init", .base = 0x4a307300,
202 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
205 .name = "l4per", .base = 0x4a307400,
206 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
210 .name = "cefuse", .base = 0x4a307600,
211 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
214 .name = "wkup", .base = 0x4a307700,
215 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
218 .name = "emu", .base = 0x4a307900,
219 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
222 .name = "device", .base = 0x4a307b00,
223 .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01,
231 .name = "mpu", .base = 0x4ae06300,
232 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
235 .name = "dsp", .base = 0x4ae06400,
236 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
237 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
240 .name = "abe", .base = 0x4ae06500,
241 .pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_nooff,
244 .name = "coreaon", .base = 0x4ae06600,
245 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
248 .name = "core", .base = 0x4ae06700,
249 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
250 .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu",
254 .name = "iva", .base = 0x4ae07200,
255 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
256 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012
259 .name = "cam", .base = 0x4ae07300,
260 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
263 .name = "dss", .base = 0x4ae07400,
264 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact
267 .name = "gpu", .base = 0x4ae07500,
268 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
271 .name = "l3init", .base = 0x4ae07600,
272 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
275 .name = "custefuse", .base = 0x4ae07700,
276 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
279 .name = "wkupaon", .base = 0x4ae07800,
280 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
283 .name = "emu", .base = 0x4ae07a00,
284 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
287 .name = "device", .base = 0x4ae07c00,
288 .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01,
296 .name = "mpu", .base = 0x4ae06300,
297 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
300 .name = "dsp1", .base = 0x4ae06400,
301 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
302 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01,
305 .name = "ipu", .base = 0x4ae06500,
306 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
307 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
311 .name = "coreaon", .base = 0x4ae06628,
312 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
315 .name = "core", .base = 0x4ae06700,
316 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
317 .rstctrl = 0x210, .rstst = 0x214, .rstmap = rst_map_012,
321 .name = "iva", .base = 0x4ae06f00,
322 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
323 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
326 .name = "cam", .base = 0x4ae07000,
327 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
330 .name = "dss", .base = 0x4ae07100,
331 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
334 .name = "gpu", .base = 0x4ae07200,
335 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
338 .name = "l3init", .base = 0x4ae07300,
339 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
340 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01,
344 .name = "l4per", .base = 0x4ae07400,
345 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
348 .name = "custefuse", .base = 0x4ae07600,
349 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
352 .name = "wkupaon", .base = 0x4ae07724,
353 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
356 .name = "emu", .base = 0x4ae07900,
357 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
360 .name = "dsp2", .base = 0x4ae07b00,
361 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
362 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
365 .name = "eve1", .base = 0x4ae07b40,
366 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
367 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
370 .name = "eve2", .base = 0x4ae07b80,
371 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
372 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
375 .name = "eve3", .base = 0x4ae07bc0,
376 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
377 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
380 .name = "eve4", .base = 0x4ae07c00,
381 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
382 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
385 .name = "rtc", .base = 0x4ae07c60,
386 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
389 .name = "vpe", .base = 0x4ae07c80,
390 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
397 { .rst = -1 },
402 { .rst = -1 },
407 .name = "per", .base = 0x44e00c00,
408 .pwrstctrl = 0xc, .pwrstst = 0x8, .dmap = &omap_prm_noinact,
409 .rstctrl = 0x0, .rstmap = am3_per_rst_map,
414 .name = "wkup", .base = 0x44e00d00,
415 .pwrstctrl = 0x4, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
416 .rstctrl = 0x0, .rstst = 0xc, .rstmap = am3_wkup_rst_map,
420 .name = "mpu", .base = 0x44e00e00,
421 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
424 .name = "device", .base = 0x44e00f00,
425 .rstctrl = 0x0, .rstst = 0x8, .rstmap = rst_map_01,
429 .name = "rtc", .base = 0x44e01000,
430 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
433 .name = "gfx", .base = 0x44e01100,
434 .pwrstctrl = 0, .pwrstst = 0x10, .dmap = &omap_prm_noinact,
435 .rstctrl = 0x4, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3",
438 .name = "cefuse", .base = 0x44e01200,
439 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
445 { .rst = 1, .st = 0 },
446 { .rst = -1 },
450 { .rst = 0, .st = 1 },
451 { .rst = 1, .st = 0 },
452 { .rst = -1 },
457 .name = "mpu", .base = 0x44df0300,
458 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
461 .name = "gfx", .base = 0x44df0400,
462 .pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
463 .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3",
466 .name = "rtc", .base = 0x44df0500,
467 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
470 .name = "tamper", .base = 0x44df0600,
471 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
474 .name = "cefuse", .base = 0x44df0700,
475 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
478 .name = "per", .base = 0x44df0800,
479 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
480 .rstctrl = 0x10, .rstst = 0x14, .rstmap = am4_per_rst_map,
484 .name = "wkup", .base = 0x44df2000,
485 .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
486 .rstctrl = 0x10, .rstst = 0x14, .rstmap = am3_wkup_rst_map,
490 .name = "device", .base = 0x44df4000,
491 .rstctrl = 0x0, .rstst = 0x4, .rstmap = am4_device_rst_map,
498 { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data },
499 { .compatible = "ti,omap5-prm-inst", .data = omap5_prm_data },
500 { .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data },
501 { .compatible = "ti,am3-prm-inst", .data = am3_prm_data },
502 { .compatible = "ti,am4-prm-inst", .data = am4_prm_data },
510 dev_dbg(prmd->dev, "%s %s: %08x/%08x\n", in omap_prm_domain_show_state()
511 prmd->pd.name, desc, in omap_prm_domain_show_state()
512 readl_relaxed(prmd->prm->base + prmd->pwrstctrl), in omap_prm_domain_show_state()
513 readl_relaxed(prmd->prm->base + prmd->pwrstst)); in omap_prm_domain_show_state()
529 if (!prmd->cap) in omap_prm_domain_power_on()
530 return 0; in omap_prm_domain_power_on()
534 if (prmd->pwrstctrl_saved) in omap_prm_domain_power_on()
535 v = prmd->pwrstctrl_saved; in omap_prm_domain_power_on()
537 v = readl_relaxed(prmd->prm->base + prmd->pwrstctrl); in omap_prm_domain_power_on()
539 if (prmd->prm->data->flags & OMAP_PRM_RET_WHEN_IDLE) in omap_prm_domain_power_on()
545 prmd->prm->base + prmd->pwrstctrl); in omap_prm_domain_power_on()
548 ret = readl_relaxed_poll_timeout(prmd->prm->base + prmd->pwrstst, in omap_prm_domain_power_on()
552 dev_err(prmd->dev, "%s: %s timed out\n", in omap_prm_domain_power_on()
553 prmd->pd.name, __func__); in omap_prm_domain_power_on()
563 return __ffs(prmd->cap->usable_modes); in omap_prm_domain_find_lowest()
573 if (!prmd->cap) in omap_prm_domain_power_off()
574 return 0; in omap_prm_domain_power_off()
578 v = readl_relaxed(prmd->prm->base + prmd->pwrstctrl); in omap_prm_domain_power_off()
579 prmd->pwrstctrl_saved = v; in omap_prm_domain_power_off()
584 if (prmd->cap->statechange) in omap_prm_domain_power_off()
586 if (prmd->cap->logicretstate) in omap_prm_domain_power_off()
591 writel_relaxed(v, prmd->prm->base + prmd->pwrstctrl); in omap_prm_domain_power_off()
594 ret = readl_relaxed_poll_timeout(prmd->prm->base + prmd->pwrstst, in omap_prm_domain_power_off()
598 dev_warn(prmd->dev, "%s: %s timed out\n", in omap_prm_domain_power_off()
599 __func__, prmd->pd.name); in omap_prm_domain_power_off()
603 return 0; in omap_prm_domain_power_off()
607 * Note that ti-sysc already manages the module clocks separately so
609 * for simple-pm-bus.
614 struct device_node *np = dev->of_node; in omap_prm_domain_attach_clock()
617 if (!of_device_is_compatible(np, "simple-pm-bus")) in omap_prm_domain_attach_clock()
618 return 0; in omap_prm_domain_attach_clock()
621 return 0; in omap_prm_domain_attach_clock()
628 if (error < 0) { in omap_prm_domain_attach_clock()
633 prmd->uses_pm_clk = 1; in omap_prm_domain_attach_clock()
635 return 0; in omap_prm_domain_attach_clock()
648 np = dev->of_node; in omap_prm_domain_attach_dev()
650 ret = of_parse_phandle_with_args(np, "power-domains", in omap_prm_domain_attach_dev()
651 "#power-domain-cells", 0, &pd_args); in omap_prm_domain_attach_dev()
652 if (ret < 0) in omap_prm_domain_attach_dev()
655 if (pd_args.args_count != 0) in omap_prm_domain_attach_dev()
656 dev_warn(dev, "%s: unusupported #power-domain-cells: %i\n", in omap_prm_domain_attach_dev()
657 prmd->pd.name, pd_args.args_count); in omap_prm_domain_attach_dev()
660 genpd_data->data = NULL; in omap_prm_domain_attach_dev()
666 return 0; in omap_prm_domain_attach_dev()
676 if (prmd->uses_pm_clk) in omap_prm_domain_detach_dev()
679 genpd_data->data = NULL; in omap_prm_domain_detach_dev()
685 struct device_node *np = dev->of_node; in omap_prm_domain_init()
690 if (!of_property_present(dev->of_node, "#power-domain-cells")) in omap_prm_domain_init()
691 return 0; in omap_prm_domain_init()
693 of_node_put(dev->of_node); in omap_prm_domain_init()
697 return -ENOMEM; in omap_prm_domain_init()
699 data = prm->data; in omap_prm_domain_init()
701 data->name); in omap_prm_domain_init()
703 return -ENOMEM; in omap_prm_domain_init()
705 prmd->dev = dev; in omap_prm_domain_init()
706 prmd->prm = prm; in omap_prm_domain_init()
707 prmd->cap = prmd->prm->data->dmap; in omap_prm_domain_init()
708 prmd->pwrstctrl = prmd->prm->data->pwrstctrl; in omap_prm_domain_init()
709 prmd->pwrstst = prmd->prm->data->pwrstst; in omap_prm_domain_init()
711 prmd->pd.name = name; in omap_prm_domain_init()
712 prmd->pd.power_on = omap_prm_domain_power_on; in omap_prm_domain_init()
713 prmd->pd.power_off = omap_prm_domain_power_off; in omap_prm_domain_init()
714 prmd->pd.attach_dev = omap_prm_domain_attach_dev; in omap_prm_domain_init()
715 prmd->pd.detach_dev = omap_prm_domain_detach_dev; in omap_prm_domain_init()
716 prmd->pd.flags = GENPD_FLAG_PM_CLK; in omap_prm_domain_init()
718 pm_genpd_init(&prmd->pd, NULL, true); in omap_prm_domain_init()
719 error = of_genpd_add_provider_simple(np, &prmd->pd); in omap_prm_domain_init()
721 pm_genpd_remove(&prmd->pd); in omap_prm_domain_init()
723 prm->prmd = prmd; in omap_prm_domain_init()
730 if (reset->mask & BIT(id)) in _is_valid_reset()
739 const struct omap_rst_map *map = reset->prm->data->rstmap; in omap_reset_get_st_bit()
741 while (map->rst >= 0) { in omap_reset_get_st_bit()
742 if (map->rst == id) in omap_reset_get_st_bit()
743 return map->st; in omap_reset_get_st_bit()
757 bool has_rstst = reset->prm->data->rstst || in omap_reset_status()
758 (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); in omap_reset_status()
762 return -ENOTSUPP; in omap_reset_status()
765 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_status()
771 * completed successfully so we can return 0 here (reset deasserted) in omap_reset_status()
773 v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); in omap_reset_status()
788 spin_lock_irqsave(&reset->lock, flags); in omap_reset_assert()
789 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_assert()
791 writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); in omap_reset_assert()
792 spin_unlock_irqrestore(&reset->lock, flags); in omap_reset_assert()
794 return 0; in omap_reset_assert()
805 struct ti_prm_platform_data *pdata = dev_get_platdata(reset->dev); in omap_reset_deassert()
806 int ret = 0; in omap_reset_deassert()
810 return 0; in omap_reset_deassert()
812 has_rstst = reset->prm->data->rstst || in omap_reset_deassert()
813 (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); in omap_reset_deassert()
820 writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); in omap_reset_deassert()
823 if (reset->clkdm) in omap_reset_deassert()
824 pdata->clkdm_deny_idle(reset->clkdm); in omap_reset_deassert()
826 /* de-assert the reset control line */ in omap_reset_deassert()
827 spin_lock_irqsave(&reset->lock, flags); in omap_reset_deassert()
828 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_deassert()
830 writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); in omap_reset_deassert()
831 spin_unlock_irqrestore(&reset->lock, flags); in omap_reset_deassert()
834 ret = readl_relaxed_poll_timeout_atomic(reset->prm->base + in omap_reset_deassert()
835 reset->prm->data->rstctrl, in omap_reset_deassert()
840 reset->prm->data->name, id); in omap_reset_deassert()
844 ret = readl_relaxed_poll_timeout_atomic(reset->prm->base + in omap_reset_deassert()
845 reset->prm->data->rstst, in omap_reset_deassert()
850 reset->prm->data->name, id); in omap_reset_deassert()
853 if (reset->clkdm) in omap_reset_deassert()
854 pdata->clkdm_allow_idle(reset->clkdm); in omap_reset_deassert()
870 if (!_is_valid_reset(reset, reset_spec->args[0])) in omap_prm_reset_xlate()
871 return -EINVAL; in omap_prm_reset_xlate()
873 return reset_spec->args[0]; in omap_prm_reset_xlate()
881 struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev); in omap_prm_reset_init()
886 * Check if we have controllable resets. If either rstctrl is non-zero in omap_prm_reset_init()
890 if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL)) in omap_prm_reset_init()
891 return 0; in omap_prm_reset_init()
894 if (!pdata || !pdata->clkdm_lookup || !pdata->clkdm_deny_idle || in omap_prm_reset_init()
895 !pdata->clkdm_allow_idle) in omap_prm_reset_init()
896 return -EINVAL; in omap_prm_reset_init()
898 map = prm->data->rstmap; in omap_prm_reset_init()
900 return -EINVAL; in omap_prm_reset_init()
902 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); in omap_prm_reset_init()
904 return -ENOMEM; in omap_prm_reset_init()
906 reset->rcdev.owner = THIS_MODULE; in omap_prm_reset_init()
907 reset->rcdev.ops = &omap_reset_ops; in omap_prm_reset_init()
908 reset->rcdev.of_node = pdev->dev.of_node; in omap_prm_reset_init()
909 reset->rcdev.nr_resets = OMAP_MAX_RESETS; in omap_prm_reset_init()
910 reset->rcdev.of_xlate = omap_prm_reset_xlate; in omap_prm_reset_init()
911 reset->rcdev.of_reset_n_cells = 1; in omap_prm_reset_init()
912 reset->dev = &pdev->dev; in omap_prm_reset_init()
913 spin_lock_init(&reset->lock); in omap_prm_reset_init()
915 reset->prm = prm; in omap_prm_reset_init()
917 sprintf(buf, "%s_clkdm", prm->data->clkdm_name ? prm->data->clkdm_name : in omap_prm_reset_init()
918 prm->data->name); in omap_prm_reset_init()
920 if (!(prm->data->flags & OMAP_PRM_HAS_NO_CLKDM)) { in omap_prm_reset_init()
921 reset->clkdm = pdata->clkdm_lookup(buf); in omap_prm_reset_init()
922 if (!reset->clkdm) in omap_prm_reset_init()
923 return -EINVAL; in omap_prm_reset_init()
926 while (map->rst >= 0) { in omap_prm_reset_init()
927 reset->mask |= BIT(map->rst); in omap_prm_reset_init()
932 if (prm->data->rstmap == rst_map_012) { in omap_prm_reset_init()
933 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_prm_reset_init()
934 if ((v & reset->mask) != reset->mask) { in omap_prm_reset_init()
935 dev_dbg(&pdev->dev, "Asserting all resets: %08x\n", v); in omap_prm_reset_init()
936 writel_relaxed(reset->mask, reset->prm->base + in omap_prm_reset_init()
937 reset->prm->data->rstctrl); in omap_prm_reset_init()
941 return devm_reset_controller_register(&pdev->dev, &reset->rcdev); in omap_prm_reset_init()
951 data = of_device_get_match_data(&pdev->dev); in omap_prm_probe()
953 return -ENOTSUPP; in omap_prm_probe()
955 prm = devm_kzalloc(&pdev->dev, sizeof(*prm), GFP_KERNEL); in omap_prm_probe()
957 return -ENOMEM; in omap_prm_probe()
959 prm->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in omap_prm_probe()
960 if (IS_ERR(prm->base)) in omap_prm_probe()
961 return PTR_ERR(prm->base); in omap_prm_probe()
963 while (data->base != res->start) { in omap_prm_probe()
964 if (!data->base) in omap_prm_probe()
965 return -EINVAL; in omap_prm_probe()
969 prm->data = data; in omap_prm_probe()
971 ret = omap_prm_domain_init(&pdev->dev, prm); in omap_prm_probe()
979 return 0; in omap_prm_probe()
982 of_genpd_del_provider(pdev->dev.of_node); in omap_prm_probe()
983 pm_genpd_remove(&prm->prmd->pd); in omap_prm_probe()