Lines Matching +full:rk3588 +full:- +full:power
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip Generic power domain support.
8 #include <linux/arm-smccc.h>
26 #include <dt-bindings/power/px30-power.h>
27 #include <dt-bindings/power/rockchip,rv1126-power.h>
28 #include <dt-bindings/power/rk3036-power.h>
29 #include <dt-bindings/power/rk3066-power.h>
30 #include <dt-bindings/power/rk3128-power.h>
31 #include <dt-bindings/power/rk3188-power.h>
32 #include <dt-bindings/power/rk3228-power.h>
33 #include <dt-bindings/power/rk3288-power.h>
34 #include <dt-bindings/power/rk3328-power.h>
35 #include <dt-bindings/power/rk3366-power.h>
36 #include <dt-bindings/power/rk3368-power.h>
37 #include <dt-bindings/power/rk3399-power.h>
38 #include <dt-bindings/power/rockchip,rk3528-power.h>
39 #include <dt-bindings/power/rockchip,rk3562-power.h>
40 #include <dt-bindings/power/rk3568-power.h>
41 #include <dt-bindings/power/rockchip,rk3576-power.h>
42 #include <dt-bindings/power/rk3588-power.h>
233 * Dynamic Memory Controller may need to coordinate with us -- see
236 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
267 mutex_lock(&pmu->mutex); in rockchip_pmu_block()
270 * Power domain clocks: Per Rockchip, we *must* keep certain clocks in rockchip_pmu_block()
271 * enabled for the duration of power-domain transitions. Most in rockchip_pmu_block()
273 * particular, DRAM DVFS / memory-controller idle) must be handled by in rockchip_pmu_block()
279 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pmu_block()
280 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_block()
283 ret = clk_bulk_enable(pd->num_clks, pd->clks); in rockchip_pmu_block()
285 dev_err(pmu->dev, in rockchip_pmu_block()
287 genpd->name, ret); in rockchip_pmu_block()
296 for (i = i - 1; i >= 0; i--) { in rockchip_pmu_block()
297 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_block()
300 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pmu_block()
303 mutex_unlock(&pmu->mutex); in rockchip_pmu_block()
320 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pmu_unblock()
321 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_unblock()
324 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pmu_unblock()
328 mutex_unlock(&pmu->mutex); in rockchip_pmu_unblock()
340 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_idle()
341 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_domain_is_idle()
344 regmap_read(pmu->regmap, pmu->info->idle_offset, &val); in rockchip_pmu_domain_is_idle()
345 return (val & pd_info->idle_mask) == pd_info->idle_mask; in rockchip_pmu_domain_is_idle()
352 regmap_read(pmu->regmap, pmu->info->ack_offset, &val); in rockchip_pmu_read_ack()
358 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_ungate_clk()
359 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_ungate_clk()
361 int clk_ungate_w_mask = pd_info->clk_ungate_mask << 16; in rockchip_pmu_ungate_clk()
363 if (!pd_info->clk_ungate_mask) in rockchip_pmu_ungate_clk()
366 if (!pmu->info->clk_ungate_offset) in rockchip_pmu_ungate_clk()
369 val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) : in rockchip_pmu_ungate_clk()
371 regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val); in rockchip_pmu_ungate_clk()
379 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_set_idle_request()
380 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pmu_set_idle_request()
381 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_set_idle_request()
382 u32 pd_req_offset = pd_info->req_offset; in rockchip_pmu_set_idle_request()
388 if (pd_info->req_mask == 0) in rockchip_pmu_set_idle_request()
390 else if (pd_info->req_w_mask) in rockchip_pmu_set_idle_request()
391 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset, in rockchip_pmu_set_idle_request()
392 idle ? (pd_info->req_mask | pd_info->req_w_mask) : in rockchip_pmu_set_idle_request()
393 pd_info->req_w_mask); in rockchip_pmu_set_idle_request()
395 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset, in rockchip_pmu_set_idle_request()
396 pd_info->req_mask, idle ? -1U : 0); in rockchip_pmu_set_idle_request()
401 target_ack = idle ? pd_info->ack_mask : 0; in rockchip_pmu_set_idle_request()
403 (val & pd_info->ack_mask) == target_ack, in rockchip_pmu_set_idle_request()
406 dev_err(pmu->dev, in rockchip_pmu_set_idle_request()
408 genpd->name, val); in rockchip_pmu_set_idle_request()
415 dev_err(pmu->dev, in rockchip_pmu_set_idle_request()
417 genpd->name, is_idle); in rockchip_pmu_set_idle_request()
428 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_save_qos()
429 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
431 &pd->qos_save_regs[0][i]); in rockchip_pmu_save_qos()
432 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
434 &pd->qos_save_regs[1][i]); in rockchip_pmu_save_qos()
435 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
437 &pd->qos_save_regs[2][i]); in rockchip_pmu_save_qos()
438 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
440 &pd->qos_save_regs[3][i]); in rockchip_pmu_save_qos()
441 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
443 &pd->qos_save_regs[4][i]); in rockchip_pmu_save_qos()
452 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_restore_qos()
453 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
455 pd->qos_save_regs[0][i]); in rockchip_pmu_restore_qos()
456 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
458 pd->qos_save_regs[1][i]); in rockchip_pmu_restore_qos()
459 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
461 pd->qos_save_regs[2][i]); in rockchip_pmu_restore_qos()
462 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
464 pd->qos_save_regs[3][i]); in rockchip_pmu_restore_qos()
465 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
467 pd->qos_save_regs[4][i]); in rockchip_pmu_restore_qos()
475 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_on()
478 if (pd->info->repair_status_mask) { in rockchip_pmu_domain_is_on()
479 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val); in rockchip_pmu_domain_is_on()
480 /* 1'b1: power on, 1'b0: power off */ in rockchip_pmu_domain_is_on()
481 return val & pd->info->repair_status_mask; in rockchip_pmu_domain_is_on()
484 /* check idle status for idle-only domains */ in rockchip_pmu_domain_is_on()
485 if (pd->info->status_mask == 0) in rockchip_pmu_domain_is_on()
488 regmap_read(pmu->regmap, pmu->info->status_offset, &val); in rockchip_pmu_domain_is_on()
490 /* 1'b0: power on, 1'b1: power off */ in rockchip_pmu_domain_is_on()
491 return !(val & pd->info->status_mask); in rockchip_pmu_domain_is_on()
496 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_mem_on()
499 regmap_read(pmu->regmap, in rockchip_pmu_domain_is_mem_on()
500 pmu->info->mem_status_offset + pd->info->mem_offset, &val); in rockchip_pmu_domain_is_mem_on()
502 /* 1'b0: power on, 1'b1: power off */ in rockchip_pmu_domain_is_mem_on()
503 return !(val & pd->info->mem_status_mask); in rockchip_pmu_domain_is_mem_on()
508 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_chain_on()
511 regmap_read(pmu->regmap, in rockchip_pmu_domain_is_chain_on()
512 pmu->info->chain_status_offset + pd->info->mem_offset, &val); in rockchip_pmu_domain_is_chain_on()
514 /* 1'b1: power on, 1'b0: power off */ in rockchip_pmu_domain_is_chain_on()
515 return val & pd->info->mem_status_mask; in rockchip_pmu_domain_is_chain_on()
520 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_mem_reset()
521 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pmu_domain_mem_reset()
528 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
530 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
536 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, in rockchip_pmu_domain_mem_reset()
537 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_pmu_domain_mem_reset()
543 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
545 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
549 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, in rockchip_pmu_domain_mem_reset()
550 pd->info->pwr_w_mask); in rockchip_pmu_domain_mem_reset()
556 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
558 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
568 struct rockchip_pmu *pmu = pd->pmu; in rockchip_do_pmu_set_power_domain()
569 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_do_pmu_set_power_domain()
570 u32 pd_pwr_offset = pd->info->pwr_offset; in rockchip_do_pmu_set_power_domain()
575 if (pd->info->pwr_mask == 0) in rockchip_do_pmu_set_power_domain()
578 if (on && pd->info->mem_status_mask) in rockchip_do_pmu_set_power_domain()
581 if (pd->info->pwr_w_mask) in rockchip_do_pmu_set_power_domain()
582 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
583 on ? pd->info->pwr_w_mask : in rockchip_do_pmu_set_power_domain()
584 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_do_pmu_set_power_domain()
586 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
587 pd->info->pwr_mask, on ? 0 : -1U); in rockchip_do_pmu_set_power_domain()
601 dev_err(pmu->dev, "failed to set domain '%s' %s, val=%d\n", in rockchip_do_pmu_set_power_domain()
602 genpd->name, on ? "on" : "off", is_on); in rockchip_do_pmu_set_power_domain()
609 pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
610 pd->info->pwr_mask, on, 0, 0, 0, &res); in rockchip_do_pmu_set_power_domain()
617 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pd_power()
620 guard(mutex)(&pmu->mutex); in rockchip_pd_power()
625 ret = clk_bulk_enable(pd->num_clks, pd->clks); in rockchip_pd_power()
627 dev_err(pmu->dev, "failed to enable clocks\n"); in rockchip_pd_power()
657 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pd_power()
664 return IS_ERR_OR_NULL(pd->supply) ? 0 : regulator_disable(pd->supply); in rockchip_pd_regulator_disable()
669 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pd_regulator_enable()
671 if (!pd->info->need_regulator) in rockchip_pd_regulator_enable()
674 if (IS_ERR_OR_NULL(pd->supply)) { in rockchip_pd_regulator_enable()
675 pd->supply = devm_of_regulator_get(pmu->dev, pd->node, "domain"); in rockchip_pd_regulator_enable()
677 if (IS_ERR(pd->supply)) in rockchip_pd_regulator_enable()
678 return PTR_ERR(pd->supply); in rockchip_pd_regulator_enable()
681 return regulator_enable(pd->supply); in rockchip_pd_regulator_enable()
691 dev_err(pd->pmu->dev, "Failed to enable supply: %d\n", ret); in rockchip_pd_power_on()
722 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name); in rockchip_pd_attach_dev()
731 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) { in rockchip_pd_attach_dev()
748 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name); in rockchip_pd_detach_dev()
765 dev_err(pmu->dev, in rockchip_pm_add_one_domain()
768 return -EINVAL; in rockchip_pm_add_one_domain()
771 if (id >= pmu->info->num_domains) { in rockchip_pm_add_one_domain()
772 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n", in rockchip_pm_add_one_domain()
774 return -EINVAL; in rockchip_pm_add_one_domain()
776 /* RK3588 has domains with two parents (RKVDEC0/RKVDEC1) */ in rockchip_pm_add_one_domain()
777 if (pmu->genpd_data.domains[id]) in rockchip_pm_add_one_domain()
780 pd_info = &pmu->info->domain_info[id]; in rockchip_pm_add_one_domain()
782 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n", in rockchip_pm_add_one_domain()
784 return -EINVAL; in rockchip_pm_add_one_domain()
787 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL); in rockchip_pm_add_one_domain()
789 return -ENOMEM; in rockchip_pm_add_one_domain()
791 pd->info = pd_info; in rockchip_pm_add_one_domain()
792 pd->pmu = pmu; in rockchip_pm_add_one_domain()
793 pd->node = node; in rockchip_pm_add_one_domain()
795 pd->num_clks = of_clk_get_parent_count(node); in rockchip_pm_add_one_domain()
796 if (pd->num_clks > 0) { in rockchip_pm_add_one_domain()
797 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, in rockchip_pm_add_one_domain()
798 sizeof(*pd->clks), GFP_KERNEL); in rockchip_pm_add_one_domain()
799 if (!pd->clks) in rockchip_pm_add_one_domain()
800 return -ENOMEM; in rockchip_pm_add_one_domain()
802 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n", in rockchip_pm_add_one_domain()
803 node, pd->num_clks); in rockchip_pm_add_one_domain()
804 pd->num_clks = 0; in rockchip_pm_add_one_domain()
807 for (i = 0; i < pd->num_clks; i++) { in rockchip_pm_add_one_domain()
808 pd->clks[i].clk = of_clk_get(node, i); in rockchip_pm_add_one_domain()
809 if (IS_ERR(pd->clks[i].clk)) { in rockchip_pm_add_one_domain()
810 error = PTR_ERR(pd->clks[i].clk); in rockchip_pm_add_one_domain()
811 dev_err(pmu->dev, in rockchip_pm_add_one_domain()
818 error = clk_bulk_prepare(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
822 pd->num_qos = of_count_phandle_with_args(node, "pm_qos", in rockchip_pm_add_one_domain()
825 if (pd->num_qos > 0) { in rockchip_pm_add_one_domain()
826 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos, in rockchip_pm_add_one_domain()
827 sizeof(*pd->qos_regmap), in rockchip_pm_add_one_domain()
829 if (!pd->qos_regmap) { in rockchip_pm_add_one_domain()
830 error = -ENOMEM; in rockchip_pm_add_one_domain()
835 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev, in rockchip_pm_add_one_domain()
836 pd->num_qos, in rockchip_pm_add_one_domain()
839 if (!pd->qos_save_regs[j]) { in rockchip_pm_add_one_domain()
840 error = -ENOMEM; in rockchip_pm_add_one_domain()
845 for (j = 0; j < pd->num_qos; j++) { in rockchip_pm_add_one_domain()
848 error = -ENODEV; in rockchip_pm_add_one_domain()
851 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node); in rockchip_pm_add_one_domain()
853 if (IS_ERR(pd->qos_regmap[j])) { in rockchip_pm_add_one_domain()
854 error = -ENODEV; in rockchip_pm_add_one_domain()
860 if (pd->info->name) in rockchip_pm_add_one_domain()
861 pd->genpd.name = pd->info->name; in rockchip_pm_add_one_domain()
863 pd->genpd.name = kbasename(node->full_name); in rockchip_pm_add_one_domain()
864 pd->genpd.power_off = rockchip_pd_power_off; in rockchip_pm_add_one_domain()
865 pd->genpd.power_on = rockchip_pd_power_on; in rockchip_pm_add_one_domain()
866 pd->genpd.attach_dev = rockchip_pd_attach_dev; in rockchip_pm_add_one_domain()
867 pd->genpd.detach_dev = rockchip_pd_detach_dev; in rockchip_pm_add_one_domain()
868 pd->genpd.flags = GENPD_FLAG_PM_CLK; in rockchip_pm_add_one_domain()
869 if (pd_info->active_wakeup) in rockchip_pm_add_one_domain()
870 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; in rockchip_pm_add_one_domain()
871 pm_genpd_init(&pd->genpd, NULL, in rockchip_pm_add_one_domain()
873 (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd))); in rockchip_pm_add_one_domain()
875 pmu->genpd_data.domains[id] = &pd->genpd; in rockchip_pm_add_one_domain()
879 clk_bulk_unprepare(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
881 clk_bulk_put(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
893 ret = pm_genpd_remove(&pd->genpd); in rockchip_pm_remove_one_domain()
895 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n", in rockchip_pm_remove_one_domain()
896 pd->genpd.name, ret); in rockchip_pm_remove_one_domain()
898 clk_bulk_unprepare(pd->num_clks, pd->clks); in rockchip_pm_remove_one_domain()
899 clk_bulk_put(pd->num_clks, pd->clks); in rockchip_pm_remove_one_domain()
901 /* protect the zeroing of pm->num_clks */ in rockchip_pm_remove_one_domain()
902 mutex_lock(&pd->pmu->mutex); in rockchip_pm_remove_one_domain()
903 pd->num_clks = 0; in rockchip_pm_remove_one_domain()
904 mutex_unlock(&pd->pmu->mutex); in rockchip_pm_remove_one_domain()
915 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pm_domain_cleanup()
916 genpd = pmu->genpd_data.domains[i]; in rockchip_pm_domain_cleanup()
930 /* First configure domain power down transition count ... */ in rockchip_configure_pd_cnt()
931 regmap_write(pmu->regmap, domain_reg_offset, count); in rockchip_configure_pd_cnt()
932 /* ... and then power up count. */ in rockchip_configure_pd_cnt()
933 regmap_write(pmu->regmap, domain_reg_offset + 4, count); in rockchip_configure_pd_cnt()
947 dev_err(pmu->dev, in rockchip_pm_add_subdomain()
952 parent_domain = pmu->genpd_data.domains[idx]; in rockchip_pm_add_subdomain()
956 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n", in rockchip_pm_add_subdomain()
963 dev_err(pmu->dev, in rockchip_pm_add_subdomain()
968 child_domain = pmu->genpd_data.domains[idx]; in rockchip_pm_add_subdomain()
972 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n", in rockchip_pm_add_subdomain()
973 parent_domain->name, child_domain->name, error); in rockchip_pm_add_subdomain()
976 dev_dbg(pmu->dev, "%s add subdomain: %s\n", in rockchip_pm_add_subdomain()
977 parent_domain->name, child_domain->name); in rockchip_pm_add_subdomain()
988 struct device *dev = &pdev->dev; in rockchip_pm_domain_probe()
989 struct device_node *np = dev->of_node; in rockchip_pm_domain_probe()
997 return -ENODEV; in rockchip_pm_domain_probe()
1003 struct_size(pmu, domains, pmu_info->num_domains), in rockchip_pm_domain_probe()
1006 return -ENOMEM; in rockchip_pm_domain_probe()
1008 pmu->dev = &pdev->dev; in rockchip_pm_domain_probe()
1009 mutex_init(&pmu->mutex); in rockchip_pm_domain_probe()
1011 pmu->info = pmu_info; in rockchip_pm_domain_probe()
1013 pmu->genpd_data.domains = pmu->domains; in rockchip_pm_domain_probe()
1014 pmu->genpd_data.num_domains = pmu_info->num_domains; in rockchip_pm_domain_probe()
1016 parent = dev->parent; in rockchip_pm_domain_probe()
1019 return -ENODEV; in rockchip_pm_domain_probe()
1022 pmu->regmap = syscon_node_to_regmap(parent->of_node); in rockchip_pm_domain_probe()
1023 if (IS_ERR(pmu->regmap)) { in rockchip_pm_domain_probe()
1025 return PTR_ERR(pmu->regmap); in rockchip_pm_domain_probe()
1029 * Configure power up and down transition delays for CORE in rockchip_pm_domain_probe()
1032 if (pmu_info->core_power_transition_time) in rockchip_pm_domain_probe()
1033 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset, in rockchip_pm_domain_probe()
1034 pmu_info->core_power_transition_time); in rockchip_pm_domain_probe()
1035 if (pmu_info->gpu_pwrcnt_offset) in rockchip_pm_domain_probe()
1036 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset, in rockchip_pm_domain_probe()
1037 pmu_info->gpu_power_transition_time); in rockchip_pm_domain_probe()
1039 error = -ENODEV; in rockchip_pm_domain_probe()
1064 dev_dbg(dev, "no power domains defined\n"); in rockchip_pm_domain_probe()
1068 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data); in rockchip_pm_domain_probe()
1437 /* ARM Trusted Firmware manages power transition times */
1521 .compatible = "rockchip,px30-power-controller",
1525 .compatible = "rockchip,rk3036-power-controller",
1529 .compatible = "rockchip,rk3066-power-controller",
1533 .compatible = "rockchip,rk3128-power-controller",
1537 .compatible = "rockchip,rk3188-power-controller",
1541 .compatible = "rockchip,rk3228-power-controller",
1545 .compatible = "rockchip,rk3288-power-controller",
1549 .compatible = "rockchip,rk3328-power-controller",
1553 .compatible = "rockchip,rk3366-power-controller",
1557 .compatible = "rockchip,rk3368-power-controller",
1561 .compatible = "rockchip,rk3399-power-controller",
1565 .compatible = "rockchip,rk3528-power-controller",
1569 .compatible = "rockchip,rk3562-power-controller",
1573 .compatible = "rockchip,rk3568-power-controller",
1577 .compatible = "rockchip,rk3576-power-controller",
1581 .compatible = "rockchip,rk3588-power-controller",
1585 .compatible = "rockchip,rv1126-power-controller",
1594 .name = "rockchip-pm-domain",
1597 * We can't forcibly eject devices from the power
1598 * domain, so we can't really remove power domains