Lines Matching +full:0 +full:x2e4
14 #define MT6893_TOP_AXI_PROT_EN_MCU_STA1 0x2e4
15 #define MT6893_TOP_AXI_PROT_EN_MCU_SET 0x2c4
16 #define MT6893_TOP_AXI_PROT_EN_MCU_CLR 0x2c8
17 #define MT6893_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4
18 #define MT6893_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8
19 #define MT6893_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0
20 #define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbb8
21 #define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbbc
22 #define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbc4
34 #define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP2 BIT(0)
43 #define MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP3 (BIT(0) | BIT(2) | BIT(4) | \
51 #define MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP1 (BIT(0) | BIT(6) | BIT(8) | \
62 #define MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP2 (BIT(0) | BIT(2) | BIT(4))
83 .ctl_offs = 0x304,
84 .pwr_sta_offs = 0x16c,
85 .pwr_sta2nd_offs = 0x170,
86 .sram_pdn_bits = 0,
87 .sram_pdn_ack_bits = 0,
110 .ctl_offs = 0x308,
111 .pwr_sta_offs = 0x16c,
112 .pwr_sta2nd_offs = 0x170,
120 .ctl_offs = 0x30c,
121 .pwr_sta_offs = 0x16c,
122 .pwr_sta2nd_offs = 0x170,
157 .ctl_offs = 0x310,
158 .pwr_sta_offs = 0x16c,
159 .pwr_sta2nd_offs = 0x170,
167 .ctl_offs = 0x314,
168 .pwr_sta_offs = 0x16c,
169 .pwr_sta2nd_offs = 0x170,
177 .ctl_offs = 0x318,
178 .pwr_sta_offs = 0x16c,
179 .pwr_sta2nd_offs = 0x170,
187 .ctl_offs = 0x31c,
188 .pwr_sta_offs = 0x16c,
189 .pwr_sta2nd_offs = 0x170,
197 .ctl_offs = 0x320,
198 .pwr_sta_offs = 0x16c,
199 .pwr_sta2nd_offs = 0x170,
207 .ctl_offs = 0x330,
208 .pwr_sta_offs = 0x16c,
209 .pwr_sta2nd_offs = 0x170,
228 .ctl_offs = 0x334,
229 .pwr_sta_offs = 0x16c,
230 .pwr_sta2nd_offs = 0x170,
249 .ctl_offs = 0x338,
250 .pwr_sta_offs = 0x16c,
251 .pwr_sta2nd_offs = 0x170,
270 .ctl_offs = 0x33c,
271 .pwr_sta_offs = 0x16c,
272 .pwr_sta2nd_offs = 0x170,
292 .ctl_offs = 0x340,
293 .pwr_sta_offs = 0x16c,
294 .pwr_sta2nd_offs = 0x170,
314 .ctl_offs = 0x344,
315 .pwr_sta_offs = 0x16c,
316 .pwr_sta2nd_offs = 0x170,
346 .ctl_offs = 0x348,
347 .pwr_sta_offs = 0x16c,
348 .pwr_sta2nd_offs = 0x170,
368 .ctl_offs = 0x34c,
369 .pwr_sta_offs = 0x16c,
370 .pwr_sta2nd_offs = 0x170,
414 .ctl_offs = 0x350,
415 .pwr_sta_offs = 0x16c,
416 .pwr_sta2nd_offs = 0x170,
445 .ctl_offs = 0x354,
446 .pwr_sta_offs = 0x16c,
447 .pwr_sta2nd_offs = 0x170,
461 .ctl_offs = 0x358,
462 .pwr_sta_offs = 0x16c,
463 .pwr_sta2nd_offs = 0x170,
477 .ctl_offs = 0x35c,
478 .pwr_sta_offs = 0x16c,
479 .pwr_sta2nd_offs = 0x170,
508 .ctl_offs = 0x360,
509 .pwr_sta_offs = 0x16c,
510 .pwr_sta2nd_offs = 0x170,
529 .ctl_offs = 0x364,
530 .pwr_sta_offs = 0x16c,
531 .pwr_sta2nd_offs = 0x170,
550 .ctl_offs = 0x368,
551 .pwr_sta_offs = 0x16c,
552 .pwr_sta2nd_offs = 0x170,
571 .ctl_offs = 0x3ac,
572 .pwr_sta_offs = 0x16c,
573 .pwr_sta2nd_offs = 0x170,