296 #define HDMI_RTX_RESET_CTL0	0x20  macro
311 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));  in imx8mp_hdmi_blk_ctrl_power_on()
318 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,  in imx8mp_hdmi_blk_ctrl_power_on()
325 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));  in imx8mp_hdmi_blk_ctrl_power_on()
329 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));  in imx8mp_hdmi_blk_ctrl_power_on()
333 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));  in imx8mp_hdmi_blk_ctrl_power_on()
341 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,  in imx8mp_hdmi_blk_ctrl_power_on()
348 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));  in imx8mp_hdmi_blk_ctrl_power_on()
356 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));  in imx8mp_hdmi_blk_ctrl_power_on()
369 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));  in imx8mp_hdmi_blk_ctrl_power_off()
372 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,  in imx8mp_hdmi_blk_ctrl_power_off()
380 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));  in imx8mp_hdmi_blk_ctrl_power_off()
384 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));  in imx8mp_hdmi_blk_ctrl_power_off()
388 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));  in imx8mp_hdmi_blk_ctrl_power_off()
393 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,  in imx8mp_hdmi_blk_ctrl_power_off()
403 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));  in imx8mp_hdmi_blk_ctrl_power_off()
411 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));  in imx8mp_hdmi_blk_ctrl_power_off()
434 	regmap_write(bc->regmap, HDMI_RTX_RESET_CTL0, 0x0);  in imx8mp_hdmi_power_notifier()
439 	regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0));  in imx8mp_hdmi_power_notifier()