Lines Matching +full:imx8mm +full:- +full:gpc
1 // SPDX-License-Identifier: GPL-2.0+
8 * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
20 #include <dt-bindings/power/imx7-power.h>
21 #include <dt-bindings/power/imx8mq-power.h>
22 #include <dt-bindings/power/imx8mm-power.h>
23 #include <dt-bindings/power/imx8mn-power.h>
24 #include <dt-bindings/power/imx8mp-power.h>
203 * (Rev. 1, 01/2018 and the older ones) GPC chapter's
322 ret = pm_runtime_get_sync(domain->dev);
324 pm_runtime_put_noidle(domain->dev);
328 if (!IS_ERR(domain->regulator)) {
329 ret = regulator_enable(domain->regulator);
331 dev_err(domain->dev,
338 reset_control_assert(domain->reset);
341 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
343 dev_err(domain->dev, "failed to enable reset clocks\n");
350 if (domain->bits.pxx) {
352 regmap_update_bits(domain->regmap, domain->regs->pup,
353 domain->bits.pxx, domain->bits.pxx);
358 ret = regmap_read_poll_timeout(domain->regmap,
359 domain->regs->pup, reg_val,
360 !(reg_val & domain->bits.pxx),
363 dev_err(domain->dev, "failed to command PGC\n");
368 for_each_set_bit(pgc, &domain->pgc, 32) {
369 regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
377 reset_control_deassert(domain->reset);
380 if (domain->bits.hskreq) {
381 regmap_update_bits(domain->regmap, domain->regs->hsk,
382 domain->bits.hskreq, domain->bits.hskreq);
385 * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val,
386 * (reg_val & domain->bits.hskack), 0,
389 * the BLK-CTL module BUS clk-en bit being set.
391 * There is a separate BLK-CTL module and we will have such a driver for it,
392 * that driver will set the BUS clk-en bit and handshake will be triggered
398 * For some BLK-CTL module (eg. AudioMix on i.MX8MP) doesn't have BUS
399 * clk-en bit, it is better to add delay here, as the BLK-CTL module
405 regmap_read_bypassed(domain->regmap, domain->regs->hsk, ®_val);
410 if (!domain->keep_clocks)
411 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
416 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
418 if (!IS_ERR(domain->regulator))
419 regulator_disable(domain->regulator);
421 pm_runtime_put(domain->dev);
433 if (!domain->keep_clocks) {
434 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
436 dev_err(domain->dev, "failed to enable reset clocks\n");
442 if (domain->bits.hskreq) {
443 regmap_clear_bits(domain->regmap, domain->regs->hsk,
444 domain->bits.hskreq);
446 ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk,
448 !(reg_val & domain->bits.hskack),
451 dev_err(domain->dev, "failed to power down ADB400\n");
456 if (domain->bits.pxx) {
458 for_each_set_bit(pgc, &domain->pgc, 32) {
459 regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
464 regmap_update_bits(domain->regmap, domain->regs->pdn,
465 domain->bits.pxx, domain->bits.pxx);
470 ret = regmap_read_poll_timeout(domain->regmap,
471 domain->regs->pdn, reg_val,
472 !(reg_val & domain->bits.pxx),
475 dev_err(domain->dev, "failed to command PGC\n");
481 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
483 if (!IS_ERR(domain->regulator)) {
484 ret = regulator_disable(domain->regulator);
486 dev_err(domain->dev,
493 pm_runtime_put_sync_suspend(domain->dev);
498 if (!domain->keep_clocks)
499 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
507 .name = "mipi-phy",
519 .name = "pcie-phy",
531 .name = "usb-hsic-phy",
597 .name = "usb-otg1",
608 .name = "usb-otg2",
670 .name = "mipi-csi1",
681 .name = "mipi-csi2",
768 .name = "usb-otg1",
780 .name = "usb-otg2",
833 .name = "vpu-g1",
844 .name = "vpu-g2",
855 .name = "vpu-h1",
937 .name = "mipi-phy1",
948 .name = "pcie-phy1",
959 .name = "usb-otg1",
970 .name = "usb-otg2",
1073 .name = "vpu-g1",
1084 .name = "vpu-g2",
1095 .name = "vpu-h1",
1120 .name = "hdmi-phy",
1131 .name = "mipi-phy2",
1156 .name = "mediamix-isp-dwp",
1247 .name = "usb-otg1",
1326 struct imx_pgc_domain *domain = pdev->dev.platform_data;
1329 domain->dev = &pdev->dev;
1331 domain->regulator = devm_regulator_get_optional(domain->dev, "power");
1332 if (IS_ERR(domain->regulator)) {
1333 if (PTR_ERR(domain->regulator) != -ENODEV)
1334 return dev_err_probe(domain->dev, PTR_ERR(domain->regulator),
1336 } else if (domain->voltage) {
1337 regulator_set_voltage(domain->regulator,
1338 domain->voltage, domain->voltage);
1341 domain->num_clks = devm_clk_bulk_get_all(domain->dev, &domain->clks);
1342 if (domain->num_clks < 0)
1343 return dev_err_probe(domain->dev, domain->num_clks,
1346 domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev);
1347 if (IS_ERR(domain->reset))
1348 return dev_err_probe(domain->dev, PTR_ERR(domain->reset),
1351 pm_runtime_enable(domain->dev);
1353 if (domain->bits.map)
1354 regmap_update_bits(domain->regmap, domain->regs->map,
1355 domain->bits.map, domain->bits.map);
1357 ret = pm_genpd_init(&domain->genpd, NULL, true);
1359 dev_err_probe(domain->dev, ret, "Failed to init power domain\n");
1364 of_property_present(domain->dev->of_node, "power-domains"))
1365 lockdep_set_subclass(&domain->genpd.mlock, 1);
1367 ret = of_genpd_add_provider_simple(domain->dev->of_node,
1368 &domain->genpd);
1370 dev_err_probe(domain->dev, ret, "Failed to add genpd provider\n");
1377 pm_genpd_remove(&domain->genpd);
1379 if (domain->bits.map)
1380 regmap_update_bits(domain->regmap, domain->regs->map,
1381 domain->bits.map, 0);
1382 pm_runtime_disable(domain->dev);
1389 struct imx_pgc_domain *domain = pdev->dev.platform_data;
1391 of_genpd_del_provider(domain->dev->of_node);
1392 pm_genpd_remove(&domain->genpd);
1394 if (domain->bits.map)
1395 regmap_update_bits(domain->regmap, domain->regs->map,
1396 domain->bits.map, 0);
1398 pm_runtime_disable(domain->dev);
1432 { "imx-pgc-domain", },
1438 .name = "imx-pgc",
1451 of_device_get_match_data(&pdev->dev);
1457 .rd_table = domain_data->reg_access_table,
1458 .wr_table = domain_data->reg_access_table,
1461 struct device *dev = &pdev->dev;
1463 of_get_child_by_name(dev->of_node, "pgc");
1470 return -EINVAL;
1498 if (domain_index >= domain_data->domains_num) {
1505 pd_pdev = platform_device_alloc("imx-pgc-domain",
1509 return -ENOMEM;
1513 &domain_data->domains[domain_index],
1514 sizeof(domain_data->domains[domain_index]));
1520 domain = pd_pdev->dev.platform_data;
1521 domain->regmap = regmap;
1522 domain->regs = domain_data->pgc_regs;
1524 domain->genpd.power_on = imx_pgc_power_up;
1525 domain->genpd.power_off = imx_pgc_power_down;
1527 pd_pdev->dev.parent = dev;
1528 device_set_node(&pd_pdev->dev, of_fwnode_handle(np));
1541 { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
1542 { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
1543 { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
1544 { .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, },
1545 { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
1551 .name = "imx-gpcv2",