Lines Matching full:bit
22 {"PSF9", BIT(0)},
23 {"RES_66", BIT(1)},
24 {"RES_67", BIT(2)},
25 {"RES_68", BIT(3)},
26 {"RES_69", BIT(4)},
27 {"RES_70", BIT(5)},
28 {"TBTLSX", BIT(6)},
43 {"USB2PLL_OFF_STS", BIT(18)},
44 {"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)},
45 {"PCIe_Gen3PLL_OFF_STS", BIT(20)},
46 {"OPIOPLL_OFF_STS", BIT(21)},
47 {"OCPLL_OFF_STS", BIT(22)},
48 {"MainPLL_OFF_STS", BIT(23)},
49 {"MIPIPLL_OFF_STS", BIT(24)},
50 {"Fast_XTAL_Osc_OFF_STS", BIT(25)},
51 {"AC_Ring_Osc_OFF_STS", BIT(26)},
52 {"MC_Ring_Osc_OFF_STS", BIT(27)},
53 {"SATAPLL_OFF_STS", BIT(29)},
54 {"XTAL_USB2PLL_OFF_STS", BIT(31)},
59 {"CSME_PG_STS", BIT(0)},
60 {"SATA_PG_STS", BIT(1)},
61 {"xHCI_PG_STS", BIT(2)},
62 {"UFSX2_PG_STS", BIT(3)},
63 {"OTG_PG_STS", BIT(5)},
64 {"SPA_PG_STS", BIT(6)},
65 {"SPB_PG_STS", BIT(7)},
66 {"SPC_PG_STS", BIT(8)},
67 {"SPD_PG_STS", BIT(9)},
68 {"SPE_PG_STS", BIT(10)},
69 {"SPF_PG_STS", BIT(11)},
70 {"LSX_PG_STS", BIT(13)},
71 {"P2SB_PG_STS", BIT(14)},
72 {"PSF_PG_STS", BIT(15)},
73 {"SBR_PG_STS", BIT(16)},
74 {"OPIDMI_PG_STS", BIT(17)},
75 {"THC0_PG_STS", BIT(18)},
76 {"THC1_PG_STS", BIT(19)},
77 {"GBETSN_PG_STS", BIT(20)},
78 {"GBE_PG_STS", BIT(21)},
79 {"LPSS_PG_STS", BIT(22)},
80 {"MMP_UFSX2_PG_STS", BIT(23)},
81 {"MMP_UFSX2B_PG_STS", BIT(24)},
82 {"FIA_PG_STS", BIT(25)},
87 {"ADSP_D3_STS", BIT(0)},
88 {"SATA_D3_STS", BIT(1)},
89 {"xHCI0_D3_STS", BIT(2)},
90 {"xDCI1_D3_STS", BIT(5)},
91 {"SDX_D3_STS", BIT(6)},
92 {"EMMC_D3_STS", BIT(7)},
93 {"IS_D3_STS", BIT(8)},
94 {"THC0_D3_STS", BIT(9)},
95 {"THC1_D3_STS", BIT(10)},
96 {"GBE_D3_STS", BIT(11)},
97 {"GBE_TSN_D3_STS", BIT(12)},
102 {"GPIO_COM0_VNN_REQ_STS", BIT(1)},
103 {"GPIO_COM1_VNN_REQ_STS", BIT(2)},
104 {"GPIO_COM2_VNN_REQ_STS", BIT(3)},
105 {"GPIO_COM3_VNN_REQ_STS", BIT(4)},
106 {"GPIO_COM4_VNN_REQ_STS", BIT(5)},
107 {"GPIO_COM5_VNN_REQ_STS", BIT(6)},
108 {"Audio_VNN_REQ_STS", BIT(7)},
109 {"ISH_VNN_REQ_STS", BIT(8)},
110 {"CNVI_VNN_REQ_STS", BIT(9)},
111 {"eSPI_VNN_REQ_STS", BIT(10)},
112 {"Display_VNN_REQ_STS", BIT(11)},
113 {"DTS_VNN_REQ_STS", BIT(12)},
114 {"SMBUS_VNN_REQ_STS", BIT(14)},
115 {"CSME_VNN_REQ_STS", BIT(15)},
116 {"SMLINK0_VNN_REQ_STS", BIT(16)},
117 {"SMLINK1_VNN_REQ_STS", BIT(17)},
118 {"CLINK_VNN_REQ_STS", BIT(20)},
119 {"DCI_VNN_REQ_STS", BIT(21)},
120 {"ITH_VNN_REQ_STS", BIT(22)},
121 {"CSME_VNN_REQ_STS", BIT(24)},
122 {"GBE_VNN_REQ_STS", BIT(25)},
127 {"CPU_C10_REQ_STS_0", BIT(0)},
128 {"PCIe_LPM_En_REQ_STS_3", BIT(3)},
129 {"ITH_REQ_STS_5", BIT(5)},
130 {"CNVI_REQ_STS_6", BIT(6)},
131 {"ISH_REQ_STS_7", BIT(7)},
132 {"USB2_SUS_PG_Sys_REQ_STS_10", BIT(10)},
133 {"PCIe_Clk_REQ_STS_12", BIT(12)},
134 {"MPHY_Core_DL_REQ_STS_16", BIT(16)},
135 {"Break-even_En_REQ_STS_17", BIT(17)},
136 {"Auto-demo_En_REQ_STS_18", BIT(18)},
137 {"MPHY_SUS_REQ_STS_22", BIT(22)},
138 {"xDCI_attached_REQ_STS_24", BIT(24)},
143 {"LSX_Wake0_En_STS", BIT(0)},
144 {"LSX_Wake0_Pol_STS", BIT(1)},
145 {"LSX_Wake1_En_STS", BIT(2)},
146 {"LSX_Wake1_Pol_STS", BIT(3)},
147 {"LSX_Wake2_En_STS", BIT(4)},
148 {"LSX_Wake2_Pol_STS", BIT(5)},
149 {"LSX_Wake3_En_STS", BIT(6)},
150 {"LSX_Wake3_Pol_STS", BIT(7)},
151 {"LSX_Wake4_En_STS", BIT(8)},
152 {"LSX_Wake4_Pol_STS", BIT(9)},
153 {"LSX_Wake5_En_STS", BIT(10)},
154 {"LSX_Wake5_Pol_STS", BIT(11)},
155 {"LSX_Wake6_En_STS", BIT(12)},
156 {"LSX_Wake6_Pol_STS", BIT(13)},
157 {"LSX_Wake7_En_STS", BIT(14)},
158 {"LSX_Wake7_Pol_STS", BIT(15)},
159 {"Intel_Se_IO_Wake0_En_STS", BIT(16)},
160 {"Intel_Se_IO_Wake0_Pol_STS", BIT(17)},
161 {"Intel_Se_IO_Wake1_En_STS", BIT(18)},
162 {"Intel_Se_IO_Wake1_Pol_STS", BIT(19)},
163 {"Int_Timer_SS_Wake0_En_STS", BIT(20)},
164 {"Int_Timer_SS_Wake0_Pol_STS", BIT(21)},
165 {"Int_Timer_SS_Wake1_En_STS", BIT(22)},
166 {"Int_Timer_SS_Wake1_Pol_STS", BIT(23)},
167 {"Int_Timer_SS_Wake2_En_STS", BIT(24)},
168 {"Int_Timer_SS_Wake2_Pol_STS", BIT(25)},
169 {"Int_Timer_SS_Wake3_En_STS", BIT(26)},
170 {"Int_Timer_SS_Wake3_Pol_STS", BIT(27)},
171 {"Int_Timer_SS_Wake4_En_STS", BIT(28)},
172 {"Int_Timer_SS_Wake4_Pol_STS", BIT(29)},
173 {"Int_Timer_SS_Wake5_En_STS", BIT(30)},
174 {"Int_Timer_SS_Wake5_Pol_STS", BIT(31)},