Lines Matching full:bit
15 {"SPI/eSPI", BIT(2)},
16 {"XHCI", BIT(3)},
17 {"SPA", BIT(4)},
18 {"SPB", BIT(5)},
19 {"SPC", BIT(6)},
20 {"GBE", BIT(7)},
22 {"SATA", BIT(0)},
23 {"HDA_PGD0", BIT(1)},
24 {"HDA_PGD1", BIT(2)},
25 {"HDA_PGD2", BIT(3)},
26 {"HDA_PGD3", BIT(4)},
27 {"SPD", BIT(5)},
28 {"LPSS", BIT(6)},
30 {"SMB", BIT(0)},
31 {"ISH", BIT(1)},
32 {"ITH", BIT(3)},
34 {"XDCI", BIT(1)},
35 {"DCI", BIT(2)},
36 {"CSE", BIT(3)},
37 {"CSME_KVM", BIT(4)},
38 {"CSME_PMT", BIT(5)},
39 {"CSME_CLINK", BIT(6)},
40 {"CSME_PTIO", BIT(7)},
42 {"CSME_USBR", BIT(0)},
43 {"CSME_SUSRAM", BIT(1)},
44 {"CSME_SMT1", BIT(2)},
45 {"CSME_SMS2", BIT(4)},
46 {"CSME_SMS1", BIT(5)},
47 {"CSME_RTC", BIT(6)},
48 {"CSME_PSF", BIT(7)},
50 {"CNVI", BIT(3)},
51 {"HDA_PGD4", BIT(2)},
52 {"HDA_PGD5", BIT(3)},
53 {"HDA_PGD6", BIT(4)},
104 {"CLKPART1_OFF_STS", BIT(0)},
105 {"CLKPART2_OFF_STS", BIT(1)},
106 {"CLKPART3_OFF_STS", BIT(2)},
107 {"CLKPART4_OFF_STS", BIT(3)},
108 {"CLKPART5_OFF_STS", BIT(4)},
109 {"CLKPART6_OFF_STS", BIT(5)},
110 {"CLKPART7_OFF_STS", BIT(6)},
111 {"CLKPART8_OFF_STS", BIT(7)},
112 {"PCIE0PLL_OFF_STS", BIT(10)},
113 {"PCIE1PLL_OFF_STS", BIT(11)},
114 {"PCIE2PLL_OFF_STS", BIT(12)},
115 {"PCIE3PLL_OFF_STS", BIT(13)},
116 {"PCIE4PLL_OFF_STS", BIT(14)},
117 {"PCIE5PLL_OFF_STS", BIT(15)},
118 {"PCIE6PLL_OFF_STS", BIT(16)},
119 {"USB2PLL_OFF_STS", BIT(18)},
120 {"OCPLL_OFF_STS", BIT(22)},
121 {"AUDIOPLL_OFF_STS", BIT(23)},
122 {"GBEPLL_OFF_STS", BIT(24)},
123 {"Fast_XTAL_Osc_OFF_STS", BIT(25)},
124 {"AC_Ring_Osc_OFF_STS", BIT(26)},
125 {"MC_Ring_Osc_OFF_STS", BIT(27)},
126 {"SATAPLL_OFF_STS", BIT(29)},
127 {"USB3PLL_OFF_STS", BIT(31)},
132 {"PMC_PGD0_PG_STS", BIT(0)},
133 {"DMI_PGD0_PG_STS", BIT(1)},
134 {"ESPISPI_PGD0_PG_STS", BIT(2)},
135 {"XHCI_PGD0_PG_STS", BIT(3)},
136 {"SPA_PGD0_PG_STS", BIT(4)},
137 {"SPB_PGD0_PG_STS", BIT(5)},
138 {"SPC_PGD0_PG_STS", BIT(6)},
139 {"GBE_PGD0_PG_STS", BIT(7)},
140 {"SATA_PGD0_PG_STS", BIT(8)},
141 {"DSP_PGD0_PG_STS", BIT(9)},
142 {"DSP_PGD1_PG_STS", BIT(10)},
143 {"DSP_PGD2_PG_STS", BIT(11)},
144 {"DSP_PGD3_PG_STS", BIT(12)},
145 {"SPD_PGD0_PG_STS", BIT(13)},
146 {"LPSS_PGD0_PG_STS", BIT(14)},
147 {"SMB_PGD0_PG_STS", BIT(16)},
148 {"ISH_PGD0_PG_STS", BIT(17)},
149 {"NPK_PGD0_PG_STS", BIT(19)},
150 {"PECI_PGD0_PG_STS", BIT(21)},
151 {"XDCI_PGD0_PG_STS", BIT(25)},
152 {"EXI_PGD0_PG_STS", BIT(26)},
153 {"CSE_PGD0_PG_STS", BIT(27)},
154 {"KVMCC_PGD0_PG_STS", BIT(28)},
155 {"PMT_PGD0_PG_STS", BIT(29)},
156 {"CLINK_PGD0_PG_STS", BIT(30)},
157 {"PTIO_PGD0_PG_STS", BIT(31)},
162 {"USBR0_PGD0_PG_STS", BIT(0)},
163 {"SMT1_PGD0_PG_STS", BIT(2)},
164 {"CSMERTC_PGD0_PG_STS", BIT(6)},
165 {"CSMEPSF_PGD0_PG_STS", BIT(7)},
166 {"CNVI_PGD0_PG_STS", BIT(19)},
167 {"DSP_PGD4_PG_STS", BIT(26)},
168 {"SPG_PGD0_PG_STS", BIT(27)},
169 {"SPE_PGD0_PG_STS", BIT(28)},
174 {"THC0_PGD0_PG_STS", BIT(7)},
175 {"THC1_PGD0_PG_STS", BIT(8)},
176 {"SPF_PGD0_PG_STS", BIT(14)},
181 {"ISH_D3_STS", BIT(2)},
182 {"LPSS_D3_STS", BIT(3)},
183 {"XDCI_D3_STS", BIT(4)},
184 {"XHCI_D3_STS", BIT(5)},
185 {"SPA_D3_STS", BIT(12)},
186 {"SPB_D3_STS", BIT(13)},
187 {"SPC_D3_STS", BIT(14)},
188 {"SPD_D3_STS", BIT(15)},
189 {"SPE_D3_STS", BIT(16)},
190 {"DSP_D3_STS", BIT(19)},
191 {"SATA_D3_STS", BIT(20)},
192 {"DMI_D3_STS", BIT(22)},
197 {"GBE_D3_STS", BIT(19)},
198 {"CNVI_D3_STS", BIT(27)},
203 {"CSMERTC_D3_STS", BIT(1)},
204 {"CSE_D3_STS", BIT(4)},
205 {"KVMCC_D3_STS", BIT(5)},
206 {"USBR0_D3_STS", BIT(6)},
207 {"SMT1_D3_STS", BIT(8)},
208 {"PTIO_D3_STS", BIT(16)},
209 {"PMT_D3_STS", BIT(17)},
214 {"THC0_D3_STS", BIT(14)},
215 {"THC1_D3_STS", BIT(15)},
220 {"ISH_VNN_REQ_STS", BIT(2)},
221 {"ESPISPI_VNN_REQ_STS", BIT(18)},
222 {"DSP_VNN_REQ_STS", BIT(19)},
227 {"NPK_VNN_REQ_STS", BIT(4)},
228 {"EXI_VNN_REQ_STS", BIT(9)},
229 {"GBE_VNN_REQ_STS", BIT(19)},
230 {"SMB_VNN_REQ_STS", BIT(25)},
231 {"CNVI_VNN_REQ_STS", BIT(27)},
236 {"CSMERTC_VNN_REQ_STS", BIT(1)},
237 {"CSE_VNN_REQ_STS", BIT(4)},
238 {"SMT1_VNN_REQ_STS", BIT(8)},
239 {"CLINK_VNN_REQ_STS", BIT(14)},
240 {"GPIOCOM4_VNN_REQ_STS", BIT(20)},
241 {"GPIOCOM3_VNN_REQ_STS", BIT(21)},
242 {"GPIOCOM2_VNN_REQ_STS", BIT(22)},
243 {"GPIOCOM1_VNN_REQ_STS", BIT(23)},
244 {"GPIOCOM0_VNN_REQ_STS", BIT(24)},
249 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},
254 {"CPU_C10_REQ_STS", BIT(0)},
255 {"PCIe_LPM_En_REQ_STS", BIT(3)},
256 {"ITH_REQ_STS", BIT(5)},
257 {"CNVI_REQ_STS", BIT(6)},
258 {"ISH_REQ_STS", BIT(7)},
259 {"USB2_SUS_PG_Sys_REQ_STS", BIT(10)},
260 {"PCIe_Clk_REQ_STS", BIT(12)},
261 {"MPHY_Core_DL_REQ_STS", BIT(16)},
262 {"Break-even_En_REQ_STS", BIT(17)},
263 {"MPHY_SUS_REQ_STS", BIT(22)},
264 {"xDCI_attached_REQ_STS", BIT(24)},