34 #define AMD_PMC_REGISTER_RESPONSE	0x980
35 #define AMD_PMC_REGISTER_ARGUMENT	0x9BC
38 #define AMD_PMC_SCRATCH_REG_CZN		0x94
39 #define AMD_PMC_SCRATCH_REG_YC		0xD14
40 #define AMD_PMC_SCRATCH_REG_1AH		0xF14
43 #define AMD_PMC_STB_PMI_0		0x03E30600
44 #define AMD_PMC_STB_S2IDLE_PREPARE	0xC6000001
45 #define AMD_PMC_STB_S2IDLE_RESTORE	0xC6000002
46 #define AMD_PMC_STB_S2IDLE_CHECK	0xC6000003
47 #define AMD_PMC_STB_DUMMY_PC		0xC6000007
50 #define AMD_S2D_REGISTER_MESSAGE	0xA20
51 #define AMD_S2D_REGISTER_RESPONSE	0xA80
52 #define AMD_S2D_REGISTER_ARGUMENT	0xA88
55 #define S2D_TELEMETRY_BYTES_MAX		0x100000U
56 #define S2D_RSVD_RAM_SPACE		0x100000
57 #define S2D_TELEMETRY_DRAMBYTES_MAX	0x1000000
60 #define STB_FORCE_FLUSH_DATA		0xCF
63 #define AMD_PMC_MAPPING_SIZE		0x01000
64 #define AMD_PMC_BASE_ADDR_OFFSET	0x10000
65 #define AMD_PMC_BASE_ADDR_LO		0x13B102E8
66 #define AMD_PMC_BASE_ADDR_HI		0x13B102EC
67 #define AMD_PMC_BASE_ADDR_LO_MASK	GENMASK(15, 0)
71 #define AMD_PMC_RESULT_OK                    0x01
72 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
73 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
74 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
75 #define AMD_PMC_RESULT_FAILED                0xFF
78 #define FCH_S0I3_ENTRY_TIME_L_OFFSET	0x30
79 #define FCH_S0I3_ENTRY_TIME_H_OFFSET	0x34
80 #define FCH_S0I3_EXIT_TIME_L_OFFSET	0x38
81 #define FCH_S0I3_EXIT_TIME_H_OFFSET	0x3C
82 #define FCH_SSC_MAPPING_SIZE		0x800
83 #define FCH_BASE_PHY_ADDR_LOW		0xFED81100
84 #define FCH_BASE_PHY_ADDR_HIGH		0x00000000
87 #define SMU_MSG_GETSMUVERSION		0x02
88 #define SMU_MSG_LOG_GETDRAM_ADDR_HI	0x04
89 #define SMU_MSG_LOG_GETDRAM_ADDR_LO	0x05
90 #define SMU_MSG_LOG_START		0x06
91 #define SMU_MSG_LOG_RESET		0x07
92 #define SMU_MSG_LOG_DUMP_DATA		0x08
93 #define SMU_MSG_GET_SUP_CONSTRAINTS	0x09
103 	MSG_TEST = 0x01,
109 	S2D_TELEMETRY_SIZE = 0x01,
127 	{"DISPLAY",	BIT(0)},
230 	return 0;  in amd_pmc_stb_debugfs_release()
256 	return 0;  in amd_pmc_stb_handle_efr()
262 	u32 fsize, num_samples, val, stb_rdptr_offset = 0;  in amd_pmc_stb_debugfs_open_v2()
274 	ret = amd_pmc_send_cmd(dev, 0, &val, STB_FORCE_FLUSH_DATA, 1);  in amd_pmc_stb_debugfs_open_v2()
289 	dev->msg_port = 0;  in amd_pmc_stb_debugfs_open_v2()
313 		/* Second copy the newer samples from offset 0 - last write */  in amd_pmc_stb_debugfs_open_v2()
321 	return 0;  in amd_pmc_stb_debugfs_open_v2()
335 	return 0;  in amd_pmc_stb_debugfs_release_v2()
353 		dev->s2d_msg_id = 0xBE;  in amd_pmc_get_ip_info()
354 		dev->smu_msg = 0x538;  in amd_pmc_get_ip_info()
358 		dev->s2d_msg_id = 0x85;  in amd_pmc_get_ip_info()
359 		dev->smu_msg = 0x538;  in amd_pmc_get_ip_info()
364 		dev->s2d_msg_id = 0xDE;  in amd_pmc_get_ip_info()
365 		dev->smu_msg = 0x938;  in amd_pmc_get_ip_info()
379 		amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true);  in amd_pmc_setup_smu_logging()
386 		amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true);  in amd_pmc_setup_smu_logging()
387 		amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true);  in amd_pmc_setup_smu_logging()
397 	amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false);  in amd_pmc_setup_smu_logging()
398 	amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false);  in amd_pmc_setup_smu_logging()
400 	return 0;  in amd_pmc_setup_smu_logging()
415 	return 0;  in get_metrics_table()
428 				table.timein_s0i3_lastcapture : 0);  in amd_pmc_validate_deepest()
439 	rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true);  in amd_pmc_get_smu_version()
443 	dev->smu_program = (val >> 24) & GENMASK(7, 0);  in amd_pmc_get_smu_version()
444 	dev->major = (val >> 16) & GENMASK(7, 0);  in amd_pmc_get_smu_version()
445 	dev->minor = (val >> 8) & GENMASK(7, 0);  in amd_pmc_get_smu_version()
446 	dev->rev = (val >> 0) & GENMASK(7, 0);  in amd_pmc_get_smu_version()
451 	return 0;  in amd_pmc_get_smu_version()
491 		return 0;  in pmc_attr_is_visible()
531 	for (idx = 0 ; idx < dev->num_ips ; idx++) {  in smu_fw_info_show()
537 	return 0;  in smu_fw_info_show()
572 	return 0;  in s0ix_stats_show()
609 		pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val);  in amd_pmc_idlemask_read()
612 		seq_printf(s, "SMU idlemask : 0x%x\n", val);  in amd_pmc_idlemask_read()
614 	return 0;  in amd_pmc_idlemask_read()
705 				val, val != 0, PMC_MSG_DELAY_MIN_US,  in amd_pmc_send_cmd()
713 	amd_pmc_reg_write(dev, response, 0);  in amd_pmc_send_cmd()
723 				val, val != 0, PMC_MSG_DELAY_MIN_US,  in amd_pmc_send_cmd()
739 		dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);  in amd_pmc_send_cmd()
743 		dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);  in amd_pmc_send_cmd()
749 		dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);  in amd_pmc_send_cmd()
781 	/* cezanne platform firmware has a fix in 64.66.0 */  in amd_pmc_wa_irq1()
790 			return 0;  in amd_pmc_wa_irq1()
795 		return 0;  in amd_pmc_wa_irq1()
803 	return 0;  in amd_pmc_wa_irq1()
822 		return 0;  in amd_pmc_verify_czn_rtc()
826 		return 0;  in amd_pmc_verify_czn_rtc()
832 		return 0;  in amd_pmc_verify_czn_rtc()
843 		return 0;  in amd_pmc_verify_czn_rtc()
852 	rc = rtc_alarm_irq_enable(rtc_device, 0);  in amd_pmc_verify_czn_rtc()
913 	return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false);  in amd_pmc_dump_data()
923 	rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false);  in amd_pmc_s2idle_restore()
959 	return 0;  in amd_pmc_suspend_handler()
982 	u32 size = 0;  in amd_pmc_s2d_init()
1009 	dev->msg_port = 0;  in amd_pmc_s2d_init()
1015 	return 0;  in amd_pmc_s2d_init()
1022 	err = amd_smn_write(0, AMD_PMC_STB_PMI_0, data);  in amd_pmc_write_stb()
1024 		dev_err(dev->dev, "failed to write data in stb: 0x%X\n", AMD_PMC_STB_PMI_0);  in amd_pmc_write_stb()
1028 	return 0;  in amd_pmc_write_stb()
1035 	for (i = 0; i < FIFO_SIZE; i++) {  in amd_pmc_read_stb()
1036 		err = amd_smn_read(0, AMD_PMC_STB_PMI_0, buf++);  in amd_pmc_read_stb()
1038 			dev_err(dev->dev, "error reading data from stb: 0x%X\n", AMD_PMC_STB_PMI_0);  in amd_pmc_read_stb()
1043 	return 0;  in amd_pmc_read_stb()
1057 	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));  in amd_pmc_probe()
1072 	err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);  in amd_pmc_probe()
1074 		dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO);  in amd_pmc_probe()
1081 	err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val);  in amd_pmc_probe()
1083 		dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI);  in amd_pmc_probe()
1122 	return 0;  in amd_pmc_probe()
1143 	{"AMDI0005", 0},
1144 	{"AMDI0006", 0},
1145 	{"AMDI0007", 0},
1146 	{"AMDI0008", 0},
1147 	{"AMDI0009", 0},
1148 	{"AMDI000A", 0},
1149 	{"AMDI000B", 0},
1150 	{"AMD0004", 0},
1151 	{"AMD0005", 0},