Lines Matching +full:7 +full:- +full:bit
1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
5 * Copyright (C) 2016-2018 Mellanox Technologies
6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
12 #include <linux/i2c-mux.h>
17 #include <linux/platform_data/i2c-mux-reg.h>
229 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0)
230 #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3)
231 #define MLXPLAT_CPLD_AGGR_MASK_DPU_BRD BIT(4)
232 #define MLXPLAT_CPLD_AGGR_MASK_DPU_CORE BIT(5)
240 #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0)
241 #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1)
242 #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2)
243 #define MLXPLAT_CPLD_AGGR_MASK_LC_SCRD BIT(3)
244 #define MLXPLAT_CPLD_AGGR_MASK_LC_SYNC BIT(4)
245 #define MLXPLAT_CPLD_AGGR_MASK_LC_ACT BIT(5)
246 #define MLXPLAT_CPLD_AGGR_MASK_LC_SDWN BIT(6)
255 #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2)
257 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6)
262 #define MLXPLAT_CPLD_PSU_XDR_MASK GENMASK(7, 0)
263 #define MLXPLAT_CPLD_PWR_XDR_MASK GENMASK(7, 0)
268 #define MLXPLAT_CPLD_FAN_XDR_MASK GENMASK(7, 0)
269 #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
277 #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0)
278 #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6)
279 #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3)
280 #define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4)
281 #define MLXPLAT_CPLD_INTRUSION_MASK BIT(6)
282 #define MLXPLAT_CPLD_PWM_PG_MASK BIT(7)
289 #define MLXPLAT_CPLD_SYS_RESET_MASK BIT(0)
292 #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1)
298 #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0)
301 #define MLXPLAT_CPLD_LPC_SM_SW_MASK GENMASK(7, 0)
303 #define MLXPLAT_CPLD_HALT_MASK BIT(3)
304 #define MLXPLAT_CPLD_RESET_MASK GENMASK(7, 1)
330 #define MLXPLAT_CPLD_NR_NONE -1
347 #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1)
348 #define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1))
350 #define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4)
352 #define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1)
353 #define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4))
354 #define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7))
355 #define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6))
378 /* mlxplat_priv - platform private data
379 * @pdev_i2c - i2c controller platform device
380 * @pdev_mux - array of mux platform devices
381 * @pdev_hotplug - hotplug platform devices
382 * @pdev_led - led platform devices
383 * @pdev_io_regs - register access platform devices
384 * @pdev_fan - FAN platform devices
385 * @pdev_wd - array of watchdog platform devices
386 * pdev_dpu - array of Data Processor Unit platform devices
434 .bit = MLXPLAT_CPLD_I2C_CAP_BIT,
459 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7
464 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7
469 static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 };
530 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
581 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
611 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
703 .mask = BIT(0),
709 .mask = BIT(1),
719 .mask = BIT(0),
725 .mask = BIT(1),
734 .mask = BIT(0),
741 .mask = BIT(1),
751 .mask = BIT(0),
757 .mask = BIT(1),
766 .mask = BIT(0),
773 .mask = BIT(1),
783 .mask = BIT(0),
790 .mask = BIT(1),
797 .mask = BIT(2),
804 .mask = BIT(3),
970 .mask = BIT(0),
976 .mask = BIT(1),
1018 .mask = BIT(0),
1024 .mask = BIT(1),
1033 .mask = BIT(0),
1040 .mask = BIT(1),
1050 .mask = BIT(0),
1056 .mask = BIT(1),
1062 .mask = BIT(2),
1068 .mask = BIT(3),
1127 .mask = BIT(0),
1133 .mask = BIT(1),
1174 .mask = BIT(0),
1180 .mask = BIT(1),
1189 .mask = BIT(0),
1191 .bit = BIT(0),
1197 .mask = BIT(1),
1199 .bit = BIT(1),
1205 .mask = BIT(2),
1207 .bit = BIT(2),
1213 .mask = BIT(3),
1215 .bit = BIT(3),
1221 .mask = BIT(4),
1223 .bit = BIT(4),
1229 .mask = BIT(5),
1231 .bit = BIT(5),
1237 .mask = BIT(6),
1239 .bit = BIT(6),
1298 .mask = BIT(0),
1304 .mask = BIT(1),
1310 .mask = BIT(2),
1316 .mask = BIT(3),
1325 .mask = BIT(0),
1332 .mask = BIT(1),
1339 .mask = BIT(2),
1346 .mask = BIT(3),
1467 .mask = BIT(0),
1474 .mask = BIT(1),
1481 .mask = BIT(2),
1488 .mask = BIT(3),
1510 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1514 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1518 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1522 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1526 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1530 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1534 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1538 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1574 .mask = BIT(0),
1584 .mask = BIT(1),
1594 .mask = BIT(2),
1604 .mask = BIT(3),
1614 .mask = BIT(4),
1624 .mask = BIT(5),
1634 .mask = BIT(6),
1639 .slot = 7,
1644 .mask = BIT(7),
1645 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1646 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1648 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1657 .mask = BIT(0),
1671 .mask = BIT(1),
1685 .mask = BIT(2),
1699 .mask = BIT(3),
1713 .mask = BIT(4),
1727 .mask = BIT(5),
1741 .mask = BIT(6),
1750 .slot = 7,
1755 .mask = BIT(7),
1760 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1761 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1763 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1772 .mask = BIT(0),
1782 .mask = BIT(1),
1792 .mask = BIT(2),
1802 .mask = BIT(3),
1812 .mask = BIT(4),
1822 .mask = BIT(5),
1832 .mask = BIT(6),
1837 .slot = 7,
1842 .mask = BIT(7),
1843 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1844 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1846 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1855 .mask = BIT(0),
1865 .mask = BIT(1),
1875 .mask = BIT(2),
1885 .mask = BIT(3),
1895 .mask = BIT(4),
1905 .mask = BIT(5),
1915 .mask = BIT(6),
1920 .slot = 7,
1925 .mask = BIT(7),
1926 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1927 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1929 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1938 .mask = BIT(0),
1948 .mask = BIT(1),
1958 .mask = BIT(2),
1968 .mask = BIT(3),
1978 .mask = BIT(4),
1988 .mask = BIT(5),
1998 .mask = BIT(6),
2003 .slot = 7,
2008 .mask = BIT(7),
2009 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
2010 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
2012 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
2021 .mask = BIT(0),
2031 .mask = BIT(1),
2041 .mask = BIT(2),
2051 .mask = BIT(3),
2061 .mask = BIT(4),
2071 .mask = BIT(5),
2081 .mask = BIT(6),
2086 .slot = 7,
2091 .mask = BIT(7),
2092 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
2093 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
2095 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
2104 .mask = BIT(0),
2114 .mask = BIT(1),
2124 .mask = BIT(2),
2134 .mask = BIT(3),
2144 .mask = BIT(4),
2154 .mask = BIT(5),
2164 .mask = BIT(6),
2169 .slot = 7,
2174 .mask = BIT(7),
2175 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
2176 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
2178 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
2341 .mask = BIT(0),
2347 .mask = BIT(1),
2356 .mask = BIT(0),
2362 .mask = BIT(1),
2432 .mask = BIT(0),
2440 .mask = BIT(1),
2448 .mask = BIT(2),
2456 .mask = BIT(3),
2464 .mask = BIT(4),
2472 .mask = BIT(5),
2480 .mask = BIT(6),
2481 .slot = 7,
2488 .mask = BIT(7),
2499 .mask = BIT(0),
2508 .mask = BIT(1),
2517 .mask = BIT(2),
2526 .mask = BIT(3),
2535 .mask = BIT(4),
2544 .mask = BIT(5),
2553 .mask = BIT(6),
2554 .slot = 7,
2562 .mask = BIT(7),
2574 .mask = BIT(0),
2577 .bit = BIT(0),
2583 .mask = BIT(1),
2586 .bit = BIT(1),
2592 .mask = BIT(2),
2595 .bit = BIT(2),
2601 .mask = BIT(3),
2604 .bit = BIT(3),
2610 .mask = BIT(4),
2613 .bit = BIT(4),
2619 .mask = BIT(5),
2622 .bit = BIT(5),
2628 .mask = BIT(6),
2629 .slot = 7,
2631 .bit = BIT(6),
2637 .mask = BIT(7),
2640 .bit = BIT(7),
2661 .mask = BIT(0),
2669 .mask = BIT(1),
2677 .mask = BIT(2),
2685 .mask = BIT(3),
2696 .mask = BIT(0),
2704 .mask = BIT(1),
2712 .mask = BIT(2),
2720 .mask = BIT(3),
2804 I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR),
2808 I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR),
2812 I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR),
2816 I2C_BOARD_INFO("mlxreg-dpu", MLXPLAT_CPLD_DPU_ADDR),
2854 dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); in mlxplat_mlxcpld_l1_switch_pwr_events_handler()
2886 err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2891 dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2892 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2895 dev_info(&mlxplat_dev->dev, "System latch is properly closed"); in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2896 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
2907 dev_err(&mlxplat_dev->dev, "Register access failed"); in mlxplat_mlxcpld_l1_switch_intrusion_events_handler()
3254 .bit = BIT(0),
3261 .bit = BIT(0),
3268 .bit = BIT(1),
3275 .bit = BIT(1),
3282 .bit = BIT(2),
3289 .bit = BIT(2),
3296 .bit = BIT(3),
3303 .bit = BIT(3),
3310 .bit = BIT(4),
3317 .bit = BIT(4),
3324 .bit = BIT(5),
3331 .bit = BIT(5),
3338 .bit = BIT(6),
3345 .bit = BIT(6),
3460 .bit = BIT(0),
3467 .bit = BIT(0),
3474 .bit = BIT(1),
3481 .bit = BIT(1),
3488 .bit = BIT(2),
3495 .bit = BIT(2),
3502 .bit = BIT(3),
3509 .bit = BIT(3),
3516 .bit = BIT(4),
3523 .bit = BIT(4),
3530 .bit = BIT(5),
3537 .bit = BIT(5),
3544 .bit = BIT(6),
3551 .bit = BIT(6),
3602 .bit = BIT(0),
3609 .bit = BIT(0),
3616 .bit = BIT(1),
3623 .bit = BIT(1),
3630 .bit = BIT(2),
3637 .bit = BIT(2),
3644 .bit = BIT(3),
3651 .bit = BIT(3),
3658 .bit = BIT(4),
3665 .bit = BIT(4),
3672 .bit = BIT(5),
3679 .bit = BIT(5),
3804 .slot = 7,
3811 .slot = 7,
3872 .bit = GENMASK(7, 0),
3878 .bit = GENMASK(7, 0),
3884 .bit = GENMASK(15, 0),
3891 .bit = GENMASK(15, 0),
3898 .bit = GENMASK(7, 0),
3904 .bit = GENMASK(7, 0),
3910 .mask = GENMASK(7, 0) & ~BIT(0),
3916 .mask = GENMASK(7, 0) & ~BIT(1),
3922 .mask = GENMASK(7, 0) & ~BIT(2),
3928 .mask = GENMASK(7, 0) & ~BIT(3),
3934 .mask = GENMASK(7, 0) & ~BIT(4),
3940 .mask = GENMASK(7, 0) & ~BIT(5),
3946 .mask = GENMASK(7, 0) & ~BIT(6),
3952 .mask = GENMASK(7, 0) & ~BIT(7),
3958 .mask = GENMASK(7, 0) & ~BIT(0),
3964 .mask = GENMASK(7, 0) & ~BIT(1),
3970 .mask = GENMASK(7, 0) & ~BIT(2),
3976 .mask = GENMASK(7, 0) & ~BIT(3),
3982 .mask = GENMASK(7, 0) & ~BIT(6),
3989 .bit = 1,
4004 .bit = GENMASK(7, 0),
4010 .bit = GENMASK(7, 0),
4016 .bit = GENMASK(15, 0),
4023 .bit = GENMASK(15, 0),
4030 .bit = GENMASK(7, 0),
4036 .bit = GENMASK(7, 0),
4042 .mask = GENMASK(7, 0) & ~BIT(0),
4048 .mask = GENMASK(7, 0) & ~BIT(1),
4054 .mask = GENMASK(7, 0) & ~BIT(2),
4060 .mask = GENMASK(7, 0) & ~BIT(3),
4066 .mask = GENMASK(7, 0) & ~BIT(4),
4072 .mask = GENMASK(7, 0) & ~BIT(5),
4078 .mask = GENMASK(7, 0) & ~BIT(6),
4084 .mask = GENMASK(7, 0) & ~BIT(6),
4090 .mask = GENMASK(7, 0) & ~BIT(0),
4096 .mask = GENMASK(7, 0) & ~BIT(1),
4102 .mask = GENMASK(7, 0) & ~BIT(2),
4108 .mask = GENMASK(7, 0) & ~BIT(3),
4114 .mask = GENMASK(7, 0) & ~BIT(6),
4121 .bit = 1,
4136 .bit = GENMASK(7, 0),
4142 .bit = GENMASK(7, 0),
4148 .bit = GENMASK(7, 0),
4154 .bit = GENMASK(7, 0),
4160 .bit = GENMASK(7, 0),
4166 .bit = GENMASK(15, 0),
4173 .bit = GENMASK(15, 0),
4180 .bit = GENMASK(15, 0),
4187 .bit = GENMASK(15, 0),
4194 .bit = GENMASK(15, 0),
4201 .bit = GENMASK(7, 0),
4207 .bit = GENMASK(7, 0),
4213 .bit = GENMASK(7, 0),
4219 .bit = GENMASK(7, 0),
4225 .bit = GENMASK(7, 0),
4231 .mask = GENMASK(7, 0) & ~BIT(3),
4237 .mask = GENMASK(7, 0) & ~BIT(2),
4243 .mask = GENMASK(7, 0) & ~BIT(6),
4249 .mask = GENMASK(7, 0) & ~BIT(7),
4255 .mask = GENMASK(7, 0) & ~BIT(1),
4262 .mask = GENMASK(7, 0) & ~BIT(6),
4268 .mask = GENMASK(7, 0) & ~BIT(7),
4274 .mask = GENMASK(7, 0) & ~BIT(4),
4281 .mask = GENMASK(7, 0) & ~BIT(5),
4288 .mask = GENMASK(7, 0) & ~BIT(0),
4294 .mask = GENMASK(7, 0) & ~BIT(1),
4300 .mask = GENMASK(7, 0) & ~BIT(2),
4306 .mask = GENMASK(7, 0) & ~BIT(3),
4312 .mask = GENMASK(7, 0) & ~BIT(5),
4318 .mask = GENMASK(7, 0) & ~BIT(6),
4324 .mask = GENMASK(7, 0) & ~BIT(7),
4330 .mask = GENMASK(7, 0) & ~BIT(0),
4336 .mask = GENMASK(7, 0) & ~BIT(3),
4342 .mask = GENMASK(7, 0) & ~BIT(4),
4348 .mask = GENMASK(7, 0) & ~BIT(5),
4354 .mask = GENMASK(7, 0) & ~BIT(6),
4360 .mask = GENMASK(7, 0) & ~BIT(0),
4366 .mask = GENMASK(7, 0) & ~BIT(1),
4372 .mask = GENMASK(7, 0) & ~BIT(2),
4378 .mask = GENMASK(7, 0) & ~BIT(3),
4384 .mask = GENMASK(7, 0) & ~BIT(5),
4390 .mask = GENMASK(7, 0) & ~BIT(6),
4396 .mask = GENMASK(7, 0) & ~BIT(7),
4402 .mask = GENMASK(7, 0) & ~BIT(0),
4408 .mask = GENMASK(7, 0) & ~BIT(1),
4414 .mask = GENMASK(7, 0) & ~BIT(2),
4420 .mask = GENMASK(7, 0) & ~BIT(3),
4426 .mask = GENMASK(7, 0) & ~BIT(5),
4432 .mask = GENMASK(7, 0) & ~BIT(6),
4439 .bit = 1,
4445 .mask = GENMASK(7, 0) & ~BIT(4),
4451 .bit = GENMASK(7, 0),
4457 .bit = GENMASK(7, 0),
4463 .bit = GENMASK(7, 0),
4469 .bit = GENMASK(7, 0),
4476 .bit = 1,
4483 .bit = 1,
4489 .bit = GENMASK(7, 0),
4495 .mask = GENMASK(7, 0) & ~BIT(4),
4501 .mask = GENMASK(7, 0) & ~BIT(5),
4507 .mask = GENMASK(7, 0) & ~BIT(6),
4513 .mask = GENMASK(7, 0) & ~BIT(7),
4520 .bit = 5,
4526 .mask = GENMASK(7, 0) & ~BIT(0),
4533 .mask = GENMASK(7, 0) & ~BIT(3),
4539 .mask = GENMASK(7, 0) & ~BIT(4),
4545 .mask = GENMASK(7, 0) & ~BIT(5),
4551 .mask = GENMASK(7, 0) & ~BIT(0),
4557 .mask = GENMASK(7, 0) & ~BIT(1),
4563 .mask = GENMASK(7, 0) & ~BIT(2),
4569 .mask = GENMASK(7, 0) & ~BIT(4),
4575 .mask = GENMASK(7, 0) & ~BIT(5),
4581 .mask = GENMASK(7, 0) & ~BIT(6),
4587 .mask = GENMASK(7, 0) & ~BIT(7),
4593 .mask = GENMASK(7, 0),
4594 .bit = 1,
4600 .bit = GENMASK(7, 0),
4606 .bit = GENMASK(7, 0),
4612 .bit = GENMASK(7, 0),
4618 .bit = GENMASK(7, 0),
4633 .bit = GENMASK(7, 0),
4639 .bit = GENMASK(7, 0),
4645 .bit = GENMASK(7, 0),
4651 .bit = GENMASK(7, 0),
4657 .bit = GENMASK(15, 0),
4664 .bit = GENMASK(15, 0),
4671 .bit = GENMASK(15, 0),
4678 .bit = GENMASK(15, 0),
4685 .bit = GENMASK(7, 0),
4691 .bit = GENMASK(7, 0),
4697 .bit = GENMASK(7, 0),
4703 .bit = GENMASK(7, 0),
4709 .mask = GENMASK(7, 0) & ~BIT(0),
4715 .mask = GENMASK(7, 0) & ~BIT(1),
4721 .mask = GENMASK(7, 0) & ~BIT(2),
4727 .mask = GENMASK(7, 0) & ~BIT(3),
4733 .mask = GENMASK(7, 0) & ~BIT(4),
4739 .mask = GENMASK(7, 0) & ~BIT(5),
4745 .mask = GENMASK(7, 0) & ~BIT(6),
4751 .mask = GENMASK(7, 0) & ~BIT(7),
4757 .mask = GENMASK(7, 0) & ~BIT(0),
4763 .mask = GENMASK(7, 0) & ~BIT(1),
4769 .mask = GENMASK(7, 0) & ~BIT(2),
4775 .mask = GENMASK(7, 0) & ~BIT(3),
4781 .mask = GENMASK(7, 0) & ~BIT(5),
4787 .mask = GENMASK(7, 0) & ~BIT(0),
4793 .mask = GENMASK(7, 0) & ~BIT(2),
4799 .mask = GENMASK(7, 0) & ~BIT(3),
4805 .mask = GENMASK(7, 0) & ~BIT(4),
4811 .mask = GENMASK(7, 0) & ~BIT(5),
4817 .mask = GENMASK(7, 0) & ~BIT(7),
4823 .mask = GENMASK(7, 0) & ~BIT(0),
4829 .mask = GENMASK(7, 0) & ~BIT(2),
4835 .mask = GENMASK(7, 0) & ~BIT(3),
4841 .mask = GENMASK(7, 0) & ~BIT(4),
4847 .mask = GENMASK(7, 0) & ~BIT(5),
4853 .mask = GENMASK(7, 0) & ~BIT(7),
4859 .mask = GENMASK(7, 0) & ~BIT(4),
4865 .mask = GENMASK(7, 0) & ~BIT(5),
4871 .mask = GENMASK(7, 0) & ~BIT(6),
4877 .mask = GENMASK(7, 0) & ~BIT(7),
4884 .bit = 5,
4890 .mask = GENMASK(7, 0) & ~BIT(3),
4896 .mask = GENMASK(7, 0) & ~BIT(4),
4902 .mask = GENMASK(7, 0) & ~BIT(5),
4908 .mask = GENMASK(7, 0) & ~BIT(0),
4914 .mask = GENMASK(7, 0) & ~BIT(1),
4920 .mask = GENMASK(7, 0) & ~BIT(2),
4926 .mask = GENMASK(7, 0) & ~BIT(3),
4932 .mask = GENMASK(7, 0) & ~BIT(4),
4938 .mask = GENMASK(7, 0) & ~BIT(5),
4944 .mask = GENMASK(7, 0) & ~BIT(6),
4950 .mask = GENMASK(7, 0) & ~BIT(7),
4956 .mask = GENMASK(7, 0) & ~BIT(0),
4962 .mask = GENMASK(7, 0) & ~BIT(1),
4968 .mask = GENMASK(7, 0) & ~BIT(2),
4974 .mask = GENMASK(7, 0) & ~BIT(3),
4980 .mask = GENMASK(7, 0) & ~BIT(4),
4986 .mask = GENMASK(7, 0) & ~BIT(5),
4992 .mask = GENMASK(7, 0) & ~BIT(6),
4998 .mask = GENMASK(7, 0) & ~BIT(7),
5005 .bit = 1,
5011 .mask = GENMASK(7, 0) & ~BIT(5),
5017 .mask = GENMASK(7, 0) & ~BIT(5),
5024 .bit = 1,
5030 .bit = GENMASK(7, 0),
5036 .mask = GENMASK(7, 0) & ~BIT(0),
5042 .mask = GENMASK(7, 0) & ~BIT(1),
5048 .mask = GENMASK(7, 0) & ~BIT(2),
5054 .mask = GENMASK(7, 0) & ~BIT(3),
5060 .mask = GENMASK(7, 0) & ~BIT(4),
5066 .mask = GENMASK(7, 0) & ~BIT(5),
5072 .mask = GENMASK(7, 0) & ~BIT(6),
5078 .mask = GENMASK(7, 0) & ~BIT(7),
5084 .bit = GENMASK(7, 0),
5090 .bit = GENMASK(7, 0),
5096 .bit = GENMASK(7, 0),
5102 .bit = GENMASK(7, 0),
5117 .bit = GENMASK(7, 0),
5123 .bit = GENMASK(15, 0),
5130 .bit = GENMASK(7, 0),
5136 .mask = GENMASK(7, 0) & ~BIT(2),
5142 .mask = GENMASK(7, 0) & ~BIT(4),
5148 .mask = GENMASK(7, 0) & ~BIT(3),
5154 .mask = GENMASK(7, 0) & ~BIT(4),
5160 .mask = GENMASK(7, 0) & ~BIT(5),
5166 .mask = GENMASK(7, 0) & ~BIT(6),
5172 .mask = GENMASK(7, 0) & ~BIT(0),
5178 .mask = GENMASK(7, 0) & ~BIT(1),
5184 .mask = GENMASK(7, 0) & ~BIT(2),
5190 .mask = GENMASK(7, 0) & ~BIT(3),
5196 .mask = GENMASK(7, 0) & ~BIT(5),
5202 .mask = GENMASK(7, 0) & ~BIT(6),
5208 .mask = GENMASK(7, 0) & ~BIT(7),
5214 .mask = GENMASK(7, 0) & ~BIT(2),
5220 .mask = GENMASK(7, 0) & ~BIT(3),
5226 .mask = GENMASK(7, 0) & ~BIT(0),
5232 .mask = GENMASK(7, 0) & ~BIT(4),
5238 .mask = GENMASK(7, 0) & ~BIT(6),
5244 .mask = GENMASK(7, 0) & ~BIT(4),
5250 .mask = GENMASK(7, 0) & ~BIT(5),
5256 .mask = GENMASK(7, 0) & ~BIT(6),
5262 .mask = GENMASK(7, 0) & ~BIT(7),
5269 .bit = 5,
5275 .mask = GENMASK(7, 0) & ~BIT(3),
5281 .mask = GENMASK(7, 0) & ~BIT(4),
5287 .mask = GENMASK(7, 0) & ~BIT(0),
5293 .bit = GENMASK(7, 0),
5299 .bit = GENMASK(7, 0),
5305 .bit = GENMASK(7, 0),
5311 .bit = GENMASK(7, 0),
5326 .bit = GENMASK(7, 0),
5332 .bit = GENMASK(7, 0),
5338 .bit = GENMASK(7, 0),
5344 .bit = GENMASK(15, 0),
5351 .bit = GENMASK(15, 0),
5358 .bit = GENMASK(15, 0),
5365 .bit = GENMASK(7, 0),
5371 .bit = GENMASK(7, 0),
5377 .bit = GENMASK(7, 0),
5383 .mask = GENMASK(7, 0) & ~BIT(1),
5389 .mask = GENMASK(7, 0) & ~BIT(3),
5395 .mask = GENMASK(7, 0) & ~BIT(4),
5401 .mask = GENMASK(7, 0) & ~BIT(0),
5407 .mask = GENMASK(7, 0) & ~BIT(1),
5413 .mask = GENMASK(7, 0) & ~BIT(2),
5419 .mask = GENMASK(7, 0) & ~BIT(3),
5425 .mask = GENMASK(7, 0) & ~BIT(0),
5431 .mask = GENMASK(7, 0) & ~BIT(1),
5437 .mask = GENMASK(7, 0) & ~BIT(2),
5443 .mask = GENMASK(7, 0) & ~BIT(3),
5449 .mask = GENMASK(7, 0) & ~BIT(0),
5455 .mask = GENMASK(7, 0) & ~BIT(1),
5461 .mask = GENMASK(7, 0) & ~BIT(2),
5467 .mask = GENMASK(7, 0) & ~BIT(3),
5473 .mask = GENMASK(7, 0) & ~BIT(6),
5479 .mask = GENMASK(7, 0) & ~BIT(7),
5485 .mask = GENMASK(7, 0) & ~BIT(0),
5491 .mask = GENMASK(7, 0) & ~BIT(2),
5497 .mask = GENMASK(7, 0) & ~BIT(3),
5503 .mask = GENMASK(7, 0) & ~BIT(4),
5509 .mask = GENMASK(7, 0) & ~BIT(5),
5515 .mask = GENMASK(7, 0) & ~BIT(7),
5521 .mask = GENMASK(7, 0) & ~BIT(0),
5527 .mask = GENMASK(7, 0) & ~BIT(1),
5533 .mask = GENMASK(7, 0) & ~BIT(2),
5539 .mask = GENMASK(7, 0) & ~BIT(3),
5545 .mask = GENMASK(7, 0) & ~BIT(6),
5552 .bit = 5,
5558 .bit = GENMASK(7, 0),
5565 .bit = 2,
5571 .mask = GENMASK(7, 0) & ~BIT(4),
5577 .mask = GENMASK(7, 0) & ~BIT(5),
5583 .mask = GENMASK(7, 0) & ~BIT(3),
5589 .mask = GENMASK(7, 0) & ~BIT(4),
5595 .mask = GENMASK(7, 0) & ~BIT(5),
5601 .bit = GENMASK(7, 0),
5607 .mask = GENMASK(7, 0) & ~BIT(0),
5613 .mask = GENMASK(7, 0) & ~BIT(1),
5619 .mask = GENMASK(7, 0) & ~BIT(2),
5625 .mask = GENMASK(7, 0) & ~BIT(3),
5631 .mask = GENMASK(7, 0) & ~BIT(0),
5637 .mask = GENMASK(7, 0) & ~BIT(1),
5643 .mask = GENMASK(7, 0) & ~BIT(2),
5649 .mask = GENMASK(7, 0) & ~BIT(3),
5656 .bit = 1,
5663 .bit = 1,
5669 .mask = GENMASK(7, 0) & ~BIT(4),
5675 .mask = GENMASK(7, 0) & ~BIT(5),
5681 .mask = GENMASK(7, 0) & ~BIT(6),
5687 .mask = GENMASK(7, 0) & ~BIT(7),
5693 .mask = GENMASK(7, 0) & ~BIT(0),
5699 .mask = GENMASK(7, 0) & ~BIT(1),
5705 .mask = GENMASK(7, 0) & ~BIT(2),
5711 .mask = GENMASK(7, 0) & ~BIT(3),
5717 .bit = GENMASK(7, 0),
5724 .bit = 1,
5730 .mask = GENMASK(7, 0) & ~BIT(0),
5736 .mask = GENMASK(7, 0) & ~BIT(1),
5742 .mask = GENMASK(7, 0) & ~BIT(0),
5748 .mask = GENMASK(7, 0) & ~BIT(1),
5754 .mask = GENMASK(7, 0) & ~BIT(7),
5760 .mask = GENMASK(7, 0),
5761 .bit = 1,
5767 .bit = GENMASK(7, 0),
5773 .bit = GENMASK(7, 0),
5779 .bit = GENMASK(7, 0),
5785 .bit = GENMASK(7, 0),
5816 .mask = GENMASK(7, 0),
5818 .bit = BIT(0),
5825 .mask = GENMASK(7, 0),
5827 .bit = BIT(1),
5833 .mask = GENMASK(7, 0),
5835 .bit = BIT(2),
5841 .mask = GENMASK(7, 0),
5843 .bit = BIT(3),
5849 .mask = GENMASK(7, 0),
5851 .bit = BIT(4),
5857 .mask = GENMASK(7, 0),
5859 .bit = BIT(5),
5865 .mask = GENMASK(7, 0),
5867 .bit = BIT(6),
5873 .mask = GENMASK(7, 0),
5875 .bit = BIT(7),
5881 .mask = GENMASK(7, 0),
5883 .bit = BIT(0),
5889 .mask = GENMASK(7, 0),
5891 .bit = BIT(1),
5897 .mask = GENMASK(7, 0),
5899 .bit = BIT(2),
5905 .mask = GENMASK(7, 0),
5907 .bit = BIT(3),
5913 .mask = GENMASK(7, 0),
5915 .bit = BIT(4),
5920 .mask = GENMASK(7, 0),
5922 .bit = BIT(5),
5945 .mask = GENMASK(7, 0),
5953 .mask = GENMASK(7, 0),
5961 .mask = GENMASK(7, 0),
5969 .mask = GENMASK(7, 0),
5977 .mask = GENMASK(7, 0),
5985 .mask = GENMASK(7, 0),
5993 .mask = GENMASK(7, 0),
5995 .slot = 7,
6001 .mask = GENMASK(7, 0),
6009 .mask = GENMASK(7, 0),
6017 .mask = GENMASK(7, 0),
6025 .mask = GENMASK(7, 0),
6033 .mask = GENMASK(7, 0),
6041 .mask = GENMASK(7, 0),
6049 .mask = GENMASK(7, 0),
6057 .mask = GENMASK(7, 0),
6065 .mask = GENMASK(7, 0),
6073 .mask = GENMASK(7, 0),
6081 .mask = GENMASK(7, 0),
6089 .mask = GENMASK(7, 0),
6097 .mask = GENMASK(7, 0),
6123 .bit = 0,
6135 .bit = 0,
6140 .mask = GENMASK(7, 0) & ~BIT(6),
6141 .bit = 6,
6150 .bit = 4,
6162 .bit = 1,
6171 .identity = "mlx-wdt-main",
6177 .identity = "mlx-wdt-aux",
6189 .bit = 0,
6206 .bit = 0,
6211 .mask = GENMASK(7, 0) & ~BIT(6),
6212 .bit = 6,
6221 .bit = 4,
6238 .bit = 4,
6247 .identity = "mlx-wdt-main",
6253 .identity = "mlx-wdt-aux",
6258 * Can be on all systems. It's differentiated by WD capability bit.
6267 .bit = 0,
6284 .bit = 0,
6289 .mask = GENMASK(7, 0) & ~BIT(6),
6290 .bit = 6,
6299 .bit = 4,
6316 .bit = 4,
6325 .identity = "mlx-wdt-main",
6331 .identity = "mlx-wdt-aux",
6855 *val = ioread8(ctx->base + reg); in mlxplat_mlxcpld_reg_read()
6864 iowrite8(val, ctx->base + reg); in mlxplat_mlxcpld_reg_write()
6967 [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"),
6990 ret = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, ®val); in mlxplat_reboot_notifier()
6993 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, in mlxplat_reboot_notifier()
7010 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK); in mlxplat_poweroff()
7016 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, in mlxplat_register_platform_device()
7038 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_default_matched()
7039 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_default_matched()
7061 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_default_wc_matched()
7062 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_default_wc_matched()
7084 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_default_eth_wc_blade_matched()
7085 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_default_eth_wc_blade_matched()
7109 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_msn21xx_matched()
7110 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_msn21xx_matched()
7132 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_msn274x_matched()
7133 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_msn274x_matched()
7155 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_msn201x_matched()
7156 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_msn201x_matched()
7178 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_qmb7xx_matched()
7179 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_qmb7xx_matched()
7204 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; in mlxplat_dmi_comex_matched()
7229 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_ng400_matched()
7230 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_ng400_matched()
7250 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR; in mlxplat_dmi_modular_matched()
7270 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_chassis_blade_matched()
7271 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_chassis_blade_matched()
7292 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_rack_switch_matched()
7293 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_rack_switch_matched()
7313 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_ng800_matched()
7314 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_ng800_matched()
7334 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_l1_switch_matched()
7335 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_l1_switch_matched()
7357 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_smart_switch_matched()
7358 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_smart_switch_matched()
7382 mlxplat_hotplug->deferred_nr = in mlxplat_dmi_ng400_hi171_matched()
7383 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; in mlxplat_dmi_ng400_hi171_matched()
7616 return -ENODEV; in mlxplat_mlxcpld_verify_bus_topology()
7621 shift = *nr - mlxplat_mux_data[i].parent; in mlxplat_mlxcpld_verify_bus_topology()
7627 mlxplat_hotplug->shift_nr = shift; in mlxplat_mlxcpld_verify_bus_topology()
7658 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, in mlxplat_lpc_cpld_device_init()
7661 err = -ENOMEM; in mlxplat_lpc_cpld_device_init()
7688 return -ENODEV; in mlxplat_pci_fpga_device_init()
7692 dev_err(&pci_dev->dev, "pci_enable_device failed with error %d\n", err); in mlxplat_pci_fpga_device_init()
7698 dev_err(&pci_dev->dev, "pci_request_regions failed with error %d\n", err); in mlxplat_pci_fpga_device_init()
7702 err = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(64)); in mlxplat_pci_fpga_device_init()
7704 err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32)); in mlxplat_pci_fpga_device_init()
7706 dev_err(&pci_dev->dev, "dma_set_mask failed with error %d\n", err); in mlxplat_pci_fpga_device_init()
7713 pci_mem_addr = devm_ioremap(&pci_dev->dev, pci_resource_start(pci_dev, 0), in mlxplat_pci_fpga_device_init()
7716 dev_err(&mlxplat_dev->dev, "ioremap failed\n"); in mlxplat_pci_fpga_device_init()
7717 err = -EIO; in mlxplat_pci_fpga_device_init()
7793 if (err == -ENODEV) in mlxplat_logicdev_init()
7813 mlxplat_hotplug->regmap = priv->regmap; in mlxplat_platdevs_init()
7814 if (priv->irq_fpga) in mlxplat_platdevs_init()
7815 mlxplat_hotplug->irq = priv->irq_fpga; in mlxplat_platdevs_init()
7816 priv->pdev_hotplug = in mlxplat_platdevs_init()
7817 platform_device_register_resndata(&mlxplat_dev->dev, in mlxplat_platdevs_init()
7818 "mlxreg-hotplug", PLATFORM_DEVID_NONE, in mlxplat_platdevs_init()
7819 priv->hotplug_resources, in mlxplat_platdevs_init()
7820 priv->hotplug_resources_size, in mlxplat_platdevs_init()
7822 if (IS_ERR(priv->pdev_hotplug)) { in mlxplat_platdevs_init()
7823 err = PTR_ERR(priv->pdev_hotplug); in mlxplat_platdevs_init()
7830 mlxplat_led->regmap = priv->regmap; in mlxplat_platdevs_init()
7831 priv->pdev_led = in mlxplat_platdevs_init()
7832 platform_device_register_resndata(&mlxplat_dev->dev, "leds-mlxreg", in mlxplat_platdevs_init()
7835 if (IS_ERR(priv->pdev_led)) { in mlxplat_platdevs_init()
7836 err = PTR_ERR(priv->pdev_led); in mlxplat_platdevs_init()
7843 mlxplat_regs_io->regmap = priv->regmap; in mlxplat_platdevs_init()
7844 priv->pdev_io_regs = platform_device_register_resndata(&mlxplat_dev->dev, in mlxplat_platdevs_init()
7845 "mlxreg-io", in mlxplat_platdevs_init()
7849 if (IS_ERR(priv->pdev_io_regs)) { in mlxplat_platdevs_init()
7850 err = PTR_ERR(priv->pdev_io_regs); in mlxplat_platdevs_init()
7857 mlxplat_fan->regmap = priv->regmap; in mlxplat_platdevs_init()
7858 priv->pdev_fan = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-fan", in mlxplat_platdevs_init()
7862 if (IS_ERR(priv->pdev_fan)) { in mlxplat_platdevs_init()
7863 err = PTR_ERR(priv->pdev_fan); in mlxplat_platdevs_init()
7869 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); in mlxplat_platdevs_init()
7874 mlxplat_wd_data[i]->regmap = priv->regmap; in mlxplat_platdevs_init()
7875 priv->pdev_wd[i] = in mlxplat_platdevs_init()
7876 platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", i, in mlxplat_platdevs_init()
7879 if (IS_ERR(priv->pdev_wd[i])) { in mlxplat_platdevs_init()
7880 err = PTR_ERR(priv->pdev_wd[i]); in mlxplat_platdevs_init()
7890 priv->pdev_dpu[i] = in mlxplat_platdevs_init()
7891 platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-dpu", in mlxplat_platdevs_init()
7894 if (IS_ERR(priv->pdev_dpu[i])) { in mlxplat_platdevs_init()
7895 err = PTR_ERR(priv->pdev_dpu[i]); in mlxplat_platdevs_init()
7903 while (i--) in mlxplat_platdevs_init()
7904 platform_device_unregister(priv->pdev_dpu[i]); in mlxplat_platdevs_init()
7906 while (i--) in mlxplat_platdevs_init()
7907 platform_device_unregister(priv->pdev_wd[i]); in mlxplat_platdevs_init()
7910 platform_device_unregister(priv->pdev_io_regs); in mlxplat_platdevs_init()
7913 platform_device_unregister(priv->pdev_led); in mlxplat_platdevs_init()
7916 platform_device_unregister(priv->pdev_hotplug); in mlxplat_platdevs_init()
7925 for (i = MLXPLAT_CPLD_DPU_MAX_DEVS - 1; i >= 0; i--) in mlxplat_platdevs_exit()
7926 platform_device_unregister(priv->pdev_dpu[i]); in mlxplat_platdevs_exit()
7927 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0; i--) in mlxplat_platdevs_exit()
7928 platform_device_unregister(priv->pdev_wd[i]); in mlxplat_platdevs_exit()
7929 if (priv->pdev_fan) in mlxplat_platdevs_exit()
7930 platform_device_unregister(priv->pdev_fan); in mlxplat_platdevs_exit()
7931 if (priv->pdev_io_regs) in mlxplat_platdevs_exit()
7932 platform_device_unregister(priv->pdev_io_regs); in mlxplat_platdevs_exit()
7933 if (priv->pdev_led) in mlxplat_platdevs_exit()
7934 platform_device_unregister(priv->pdev_led); in mlxplat_platdevs_exit()
7935 if (priv->pdev_hotplug) in mlxplat_platdevs_exit()
7936 platform_device_unregister(priv->pdev_hotplug); in mlxplat_platdevs_exit()
7952 if (!priv->pdev_i2c) { in mlxplat_i2c_mux_topology_init()
7953 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_NOTIFIED; in mlxplat_i2c_mux_topology_init()
7957 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED; in mlxplat_i2c_mux_topology_init()
7959 priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, in mlxplat_i2c_mux_topology_init()
7960 "i2c-mux-reg", i, NULL, 0, in mlxplat_i2c_mux_topology_init()
7963 if (IS_ERR(priv->pdev_mux[i])) { in mlxplat_i2c_mux_topology_init()
7964 err = PTR_ERR(priv->pdev_mux[i]); in mlxplat_i2c_mux_topology_init()
7972 while (i--) in mlxplat_i2c_mux_topology_init()
7973 platform_device_unregister(priv->pdev_mux[i]); in mlxplat_i2c_mux_topology_init()
7981 for (i = mlxplat_mux_num - 1; i >= 0; i--) { in mlxplat_i2c_mux_topology_exit()
7982 if (priv->pdev_mux[i]) in mlxplat_i2c_mux_topology_exit()
7983 platform_device_unregister(priv->pdev_mux[i]); in mlxplat_i2c_mux_topology_exit()
8005 nr = (nr == mlxplat_max_adap_num) ? -1 : nr; in mlxplat_i2c_main_init()
8006 mlxplat_i2c->regmap = priv->regmap; in mlxplat_i2c_main_init()
8007 mlxplat_i2c->handle = priv; in mlxplat_i2c_main_init()
8009 /* Set mapped base address of I2C-LPC bridge over PCIe */ in mlxplat_i2c_main_init()
8011 mlxplat_i2c->addr = i2c_bridge_addr; in mlxplat_i2c_main_init()
8012 priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", in mlxplat_i2c_main_init()
8013 nr, priv->hotplug_resources, in mlxplat_i2c_main_init()
8014 priv->hotplug_resources_size, in mlxplat_i2c_main_init()
8016 if (IS_ERR(priv->pdev_i2c)) { in mlxplat_i2c_main_init()
8017 err = PTR_ERR(priv->pdev_i2c); in mlxplat_i2c_main_init()
8021 if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) { in mlxplat_i2c_main_init()
8030 platform_device_unregister(priv->pdev_i2c); in mlxplat_i2c_main_init()
8040 if (priv->pdev_i2c) in mlxplat_i2c_main_exit()
8041 platform_device_unregister(priv->pdev_i2c); in mlxplat_i2c_main_exit()
8052 acpi_dev = ACPI_COMPANION(&pdev->dev); in mlxplat_probe()
8056 return -ENODEV; in mlxplat_probe()
8064 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), in mlxplat_probe()
8067 err = -ENOMEM; in mlxplat_probe()
8071 priv->hotplug_resources = hotplug_resources; in mlxplat_probe()
8072 priv->hotplug_resources_size = hotplug_resources_size; in mlxplat_probe()
8073 priv->irq_fpga = irq_fpga; in mlxplat_probe()
8078 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, in mlxplat_probe()
8081 if (IS_ERR(priv->regmap)) { in mlxplat_probe()
8082 err = PTR_ERR(priv->regmap); in mlxplat_probe()
8087 for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { in mlxplat_probe()
8088 err = regmap_write(priv->regmap, in mlxplat_probe()
8089 mlxplat_regmap_config->reg_defaults[i].reg, in mlxplat_probe()
8090 mlxplat_regmap_config->reg_defaults[i].def); in mlxplat_probe()
8100 regcache_mark_dirty(priv->regmap); in mlxplat_probe()
8101 err = regcache_sync(priv->regmap); in mlxplat_probe()
8157 return -ENODEV; in mlxplat_init()