Lines Matching +full:hid +full:- +full:over +full:- +full:spi
1 # SPDX-License-Identifier: GPL-2.0-only
26 If you have an ACPI-compatible Chromebook, say Y or M here.
47 The range of memory used is 0xf00000-0x1000000, traditionally
73 devices that have multiple drop-in options for one component.
94 EC through an I2C bus. This uses a simple byte-level protocol with
103 through rpmsg. This uses a simple byte-level protocol with a
104 checksum. Also since there's no addition EC-to-host interrupt, this
117 ISH Transport protocol (ISH-TP). This uses a simple byte-level
124 tristate "ChromeOS Embedded Controller (SPI)"
125 depends on CROS_EC && SPI
129 through a SPI bus, using a byte-level protocol. Since the EC's
131 'pre-amble' bytes before the response actually starts.
138 through a UART, using a byte-level protocol.
149 over an LPC bus, including the LPC Microchip EC (MEC) variant.
150 This uses a simple byte-level protocol with a checksum. This is
246 tristate "ChromeOS EC Type-C Connector Control"
258 called cros-ec-typec.
262 depends on HID && I2C && PM
283 tristate "ChromeOS Type-C power delivery event notifier"
287 If you say Y here, you get support for Type-C PD event notifications
302 This driver provides the support needed for the in-built electronic
308 tristate "ChromeOS EC Type-C Switch Control"
312 If you say Y here, you get support for configuring the ChromeOS EC Type-C