Lines Matching +full:pin +full:- +full:val
1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include "pinctrl-common.h"
19 #include "../pinctrl-utils.h"
42 const struct visconti_desc_pin *pin = &priv->devdata->pins[_pin]; in visconti_pin_config_set() local
46 unsigned int val, set_val, pude_val; in visconti_pin_config_set() local
49 dev_dbg(priv->dev, "%s: pin = %d (%s)\n", __func__, _pin, pin->pin.name); in visconti_pin_config_set()
51 spin_lock_irqsave(&priv->lock, flags); in visconti_pin_config_set()
64 val = readl(priv->base + pin->pudsel_offset); in visconti_pin_config_set()
65 val &= ~BIT(pin->pud_shift); in visconti_pin_config_set()
66 val |= set_val << pin->pud_shift; in visconti_pin_config_set()
67 writel(val, priv->base + pin->pudsel_offset); in visconti_pin_config_set()
72 val = readl(priv->base + pin->pude_offset); in visconti_pin_config_set()
73 val &= ~BIT(pin->pud_shift); in visconti_pin_config_set()
74 val |= pude_val << pin->pud_shift; in visconti_pin_config_set()
75 writel(val, priv->base + pin->pude_offset); in visconti_pin_config_set()
76 dev_dbg(priv->dev, "BIAS(%d): off = 0x%x val = 0x%x\n", in visconti_pin_config_set()
77 param, pin->pude_offset, val); in visconti_pin_config_set()
82 dev_dbg(priv->dev, "DRV_STR arg = %d\n", arg); in visconti_pin_config_set()
99 set_val = DIV_ROUND_CLOSEST(arg, 2) - 1; in visconti_pin_config_set()
102 ret = -EINVAL; in visconti_pin_config_set()
106 val = readl(priv->base + pin->dsel_offset); in visconti_pin_config_set()
107 val &= ~(DSEL_MASK << pin->dsel_shift); in visconti_pin_config_set()
108 val |= set_val << pin->dsel_shift; in visconti_pin_config_set()
109 writel(val, priv->base + pin->dsel_offset); in visconti_pin_config_set()
113 ret = -EOPNOTSUPP; in visconti_pin_config_set()
118 spin_unlock_irqrestore(&priv->lock, flags); in visconti_pin_config_set()
132 pins = priv->devdata->groups[selector].pins; in visconti_pin_config_group_set()
133 num_pins = priv->devdata->groups[selector].nr_pins; in visconti_pin_config_group_set()
135 dev_dbg(priv->dev, "%s: select = %d, n_pin = %d, n_config = %d\n", in visconti_pin_config_group_set()
159 return priv->devdata->nr_groups; in visconti_get_groups_count()
167 return priv->devdata->groups[selector].name; in visconti_get_group_name()
177 *pins = priv->devdata->groups[selector].pins; in visconti_get_group_pins()
178 *num_pins = priv->devdata->groups[selector].nr_pins; in visconti_get_group_pins()
196 return priv->devdata->nr_functions; in visconti_get_functions_count()
204 return priv->devdata->functions[selector].name; in visconti_get_function_name()
214 *groups = priv->devdata->functions[selector].groups; in visconti_get_function_groups()
215 *num_groups = priv->devdata->functions[selector].nr_groups; in visconti_get_function_groups()
224 const struct visconti_pin_function *func = &priv->devdata->functions[function]; in visconti_set_mux()
225 const struct visconti_pin_group *grp = &priv->devdata->groups[group]; in visconti_set_mux()
226 const struct visconti_mux *mux = &grp->mux; in visconti_set_mux()
227 unsigned int val; in visconti_set_mux() local
230 dev_dbg(priv->dev, "%s: function = %d(%s) group = %d(%s)\n", __func__, in visconti_set_mux()
231 function, func->name, group, grp->name); in visconti_set_mux()
233 spin_lock_irqsave(&priv->lock, flags); in visconti_set_mux()
236 val = readl(priv->base + mux->offset); in visconti_set_mux()
237 val &= ~mux->mask; in visconti_set_mux()
238 val |= mux->val; in visconti_set_mux()
239 writel(val, priv->base + mux->offset); in visconti_set_mux()
241 spin_unlock_irqrestore(&priv->lock, flags); in visconti_set_mux()
243 dev_dbg(priv->dev, "[%x]: 0x%x\n", mux->offset, val); in visconti_set_mux()
250 unsigned int pin) in visconti_gpio_request_enable() argument
253 const struct visconti_mux *gpio_mux = &priv->devdata->gpio_mux[pin]; in visconti_gpio_request_enable()
255 unsigned int val; in visconti_gpio_request_enable() local
257 dev_dbg(priv->dev, "%s: pin = %d\n", __func__, pin); in visconti_gpio_request_enable()
260 spin_lock_irqsave(&priv->lock, flags); in visconti_gpio_request_enable()
261 val = readl(priv->base + gpio_mux->offset); in visconti_gpio_request_enable()
262 val &= ~gpio_mux->mask; in visconti_gpio_request_enable()
263 val |= gpio_mux->val; in visconti_gpio_request_enable()
264 writel(val, priv->base + gpio_mux->offset); in visconti_gpio_request_enable()
265 spin_unlock_irqrestore(&priv->lock, flags); in visconti_gpio_request_enable()
282 struct device *dev = &pdev->dev; in visconti_pinctrl_probe()
289 return -ENOMEM; in visconti_pinctrl_probe()
291 priv->dev = dev; in visconti_pinctrl_probe()
292 priv->devdata = devdata; in visconti_pinctrl_probe()
293 spin_lock_init(&priv->lock); in visconti_pinctrl_probe()
295 priv->base = devm_platform_ioremap_resource(pdev, 0); in visconti_pinctrl_probe()
296 if (IS_ERR(priv->base)) { in visconti_pinctrl_probe()
298 return PTR_ERR(priv->base); in visconti_pinctrl_probe()
301 pins = devm_kcalloc(dev, devdata->nr_pins, in visconti_pinctrl_probe()
304 return -ENOMEM; in visconti_pinctrl_probe()
306 for (i = 0; i < devdata->nr_pins; i++) in visconti_pinctrl_probe()
307 pins[i] = devdata->pins[i].pin; in visconti_pinctrl_probe()
309 priv->pctl_desc.name = dev_name(dev); in visconti_pinctrl_probe()
310 priv->pctl_desc.owner = THIS_MODULE; in visconti_pinctrl_probe()
311 priv->pctl_desc.pins = pins; in visconti_pinctrl_probe()
312 priv->pctl_desc.npins = devdata->nr_pins; in visconti_pinctrl_probe()
313 priv->pctl_desc.confops = &visconti_pinconf_ops; in visconti_pinctrl_probe()
314 priv->pctl_desc.pctlops = &visconti_pinctrl_ops; in visconti_pinctrl_probe()
315 priv->pctl_desc.pmxops = &visconti_pinmux_ops; in visconti_pinctrl_probe()
317 ret = devm_pinctrl_register_and_init(dev, &priv->pctl_desc, in visconti_pinctrl_probe()
318 priv, &priv->pctl); in visconti_pinctrl_probe()
324 if (devdata->unlock) in visconti_pinctrl_probe()
325 devdata->unlock(priv->base); in visconti_pinctrl_probe()
327 return pinctrl_enable(priv->pctl); in visconti_pinctrl_probe()