1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
10  * Copyright (C) 2009-2011 ST-Ericsson AB
27 #include "../pinctrl-utils.h"
28 #include "pinctrl-tegra.h"
32 	return readl(pmx->regs[bank] + reg);  in pmx_readl()
37 	writel_relaxed(val, pmx->regs[bank] + reg);  in pmx_writel()
46 	return pmx->soc->ngroups;  in tegra_pinctrl_get_groups_count()
54 	return pmx->soc->groups[group].name;  in tegra_pinctrl_get_group_name()
64 	*pins = pmx->soc->groups[group].pins;  in tegra_pinctrl_get_group_pins()
65 	*num_pins = pmx->soc->groups[group].npins;  in tegra_pinctrl_get_group_pins()
75 	seq_printf(s, " %s", dev_name(pctldev->dev));  in tegra_pinctrl_pin_dbg_show()
85 	{"nvidia,enable-input",		TEGRA_PINCONF_PARAM_ENABLE_INPUT},
86 	{"nvidia,open-drain",		TEGRA_PINCONF_PARAM_OPEN_DRAIN},
88 	{"nvidia,io-reset",		TEGRA_PINCONF_PARAM_IORESET},
89 	{"nvidia,rcv-sel",		TEGRA_PINCONF_PARAM_RCV_SEL},
90 	{"nvidia,io-hv",		TEGRA_PINCONF_PARAM_RCV_SEL},
91 	{"nvidia,high-speed-mode",	TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
93 	{"nvidia,low-power-mode",	TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
94 	{"nvidia,pull-down-strength",	TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
95 	{"nvidia,pull-up-strength",	TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
96 	{"nvidia,slew-rate-falling",	TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
97 	{"nvidia,slew-rate-rising",	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
98 	{"nvidia,drive-type",		TEGRA_PINCONF_PARAM_DRIVE_TYPE},
107 	struct device *dev = pctldev->dev;  in tegra_pinctrl_dt_subnode_to_map()
121 		if (ret != -EINVAL)  in tegra_pinctrl_dt_subnode_to_map()
136 		} else if (ret != -EINVAL) {  in tegra_pinctrl_dt_subnode_to_map()
225 	return pmx->soc->nfunctions;  in tegra_pinctrl_get_funcs_count()
233 	return pmx->functions[function].name;  in tegra_pinctrl_get_func_name()
243 	*groups = pmx->functions[function].groups;  in tegra_pinctrl_get_func_groups()
244 	*num_groups = pmx->functions[function].ngroups;  in tegra_pinctrl_get_func_groups()
258 	g = &pmx->soc->groups[group];  in tegra_pinctrl_set_mux()
260 	if (WARN_ON(g->mux_reg < 0))  in tegra_pinctrl_set_mux()
261 		return -EINVAL;  in tegra_pinctrl_set_mux()
263 	for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {  in tegra_pinctrl_set_mux()
264 		if (g->funcs[i] == function)  in tegra_pinctrl_set_mux()
267 	if (WARN_ON(i == ARRAY_SIZE(g->funcs)))  in tegra_pinctrl_set_mux()
268 		return -EINVAL;  in tegra_pinctrl_set_mux()
270 	val = pmx_readl(pmx, g->mux_bank, g->mux_reg);  in tegra_pinctrl_set_mux()
271 	val &= ~(0x3 << g->mux_bit);  in tegra_pinctrl_set_mux()
272 	val |= i << g->mux_bit;  in tegra_pinctrl_set_mux()
273 	pmx_writel(pmx, val, g->mux_bank, g->mux_reg);  in tegra_pinctrl_set_mux()
286 	for (group = 0; group < pmx->soc->ngroups; ++group) {  in tegra_pinctrl_get_group()
292 				return &pmx->soc->groups[group];  in tegra_pinctrl_get_group()
296 	dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset);  in tegra_pinctrl_get_group()
308 	if (!pmx->soc->sfsel_in_mux)  in tegra_pinctrl_gpio_request_enable()
314 		return -EINVAL;  in tegra_pinctrl_gpio_request_enable()
316 	if (group->mux_reg < 0 || group->sfsel_bit < 0)  in tegra_pinctrl_gpio_request_enable()
317 		return -EINVAL;  in tegra_pinctrl_gpio_request_enable()
319 	value = pmx_readl(pmx, group->mux_bank, group->mux_reg);  in tegra_pinctrl_gpio_request_enable()
320 	value &= ~BIT(group->sfsel_bit);  in tegra_pinctrl_gpio_request_enable()
321 	pmx_writel(pmx, value, group->mux_bank, group->mux_reg);  in tegra_pinctrl_gpio_request_enable()
334 	if (!pmx->soc->sfsel_in_mux)  in tegra_pinctrl_gpio_disable_free()
342 	if (group->mux_reg < 0 || group->sfsel_bit < 0)  in tegra_pinctrl_gpio_disable_free()
345 	value = pmx_readl(pmx, group->mux_bank, group->mux_reg);  in tegra_pinctrl_gpio_disable_free()
346 	value |= BIT(group->sfsel_bit);  in tegra_pinctrl_gpio_disable_free()
347 	pmx_writel(pmx, value, group->mux_bank, group->mux_reg);  in tegra_pinctrl_gpio_disable_free()
367 		*bank = g->pupd_bank;  in tegra_pinconf_reg()
368 		*reg = g->pupd_reg;  in tegra_pinconf_reg()
369 		*bit = g->pupd_bit;  in tegra_pinconf_reg()
373 		*bank = g->tri_bank;  in tegra_pinconf_reg()
374 		*reg = g->tri_reg;  in tegra_pinconf_reg()
375 		*bit = g->tri_bit;  in tegra_pinconf_reg()
379 		*bank = g->mux_bank;  in tegra_pinconf_reg()
380 		*reg = g->mux_reg;  in tegra_pinconf_reg()
381 		*bit = g->einput_bit;  in tegra_pinconf_reg()
385 		*bank = g->mux_bank;  in tegra_pinconf_reg()
386 		*reg = g->mux_reg;  in tegra_pinconf_reg()
387 		*bit = g->odrain_bit;  in tegra_pinconf_reg()
391 		*bank = g->mux_bank;  in tegra_pinconf_reg()
392 		*reg = g->mux_reg;  in tegra_pinconf_reg()
393 		*bit = g->lock_bit;  in tegra_pinconf_reg()
397 		*bank = g->mux_bank;  in tegra_pinconf_reg()
398 		*reg = g->mux_reg;  in tegra_pinconf_reg()
399 		*bit = g->ioreset_bit;  in tegra_pinconf_reg()
403 		*bank = g->mux_bank;  in tegra_pinconf_reg()
404 		*reg = g->mux_reg;  in tegra_pinconf_reg()
405 		*bit = g->rcv_sel_bit;  in tegra_pinconf_reg()
409 		if (pmx->soc->hsm_in_mux) {  in tegra_pinconf_reg()
410 			*bank = g->mux_bank;  in tegra_pinconf_reg()
411 			*reg = g->mux_reg;  in tegra_pinconf_reg()
413 			*bank = g->drv_bank;  in tegra_pinconf_reg()
414 			*reg = g->drv_reg;  in tegra_pinconf_reg()
416 		*bit = g->hsm_bit;  in tegra_pinconf_reg()
420 		if (pmx->soc->schmitt_in_mux) {  in tegra_pinconf_reg()
421 			*bank = g->mux_bank;  in tegra_pinconf_reg()
422 			*reg = g->mux_reg;  in tegra_pinconf_reg()
424 			*bank = g->drv_bank;  in tegra_pinconf_reg()
425 			*reg = g->drv_reg;  in tegra_pinconf_reg()
427 		*bit = g->schmitt_bit;  in tegra_pinconf_reg()
431 		*bank = g->drv_bank;  in tegra_pinconf_reg()
432 		*reg = g->drv_reg;  in tegra_pinconf_reg()
433 		*bit = g->lpmd_bit;  in tegra_pinconf_reg()
437 		*bank = g->drv_bank;  in tegra_pinconf_reg()
438 		*reg = g->drv_reg;  in tegra_pinconf_reg()
439 		*bit = g->drvdn_bit;  in tegra_pinconf_reg()
440 		*width = g->drvdn_width;  in tegra_pinconf_reg()
443 		*bank = g->drv_bank;  in tegra_pinconf_reg()
444 		*reg = g->drv_reg;  in tegra_pinconf_reg()
445 		*bit = g->drvup_bit;  in tegra_pinconf_reg()
446 		*width = g->drvup_width;  in tegra_pinconf_reg()
449 		*bank = g->drv_bank;  in tegra_pinconf_reg()
450 		*reg = g->drv_reg;  in tegra_pinconf_reg()
451 		*bit = g->slwf_bit;  in tegra_pinconf_reg()
452 		*width = g->slwf_width;  in tegra_pinconf_reg()
455 		*bank = g->drv_bank;  in tegra_pinconf_reg()
456 		*reg = g->drv_reg;  in tegra_pinconf_reg()
457 		*bit = g->slwr_bit;  in tegra_pinconf_reg()
458 		*width = g->slwr_width;  in tegra_pinconf_reg()
461 		if (pmx->soc->drvtype_in_mux) {  in tegra_pinconf_reg()
462 			*bank = g->mux_bank;  in tegra_pinconf_reg()
463 			*reg = g->mux_reg;  in tegra_pinconf_reg()
465 			*bank = g->drv_bank;  in tegra_pinconf_reg()
466 			*reg = g->drv_reg;  in tegra_pinconf_reg()
468 		*bit = g->drvtype_bit;  in tegra_pinconf_reg()
472 		dev_err(pmx->dev, "Invalid config param %04x\n", param);  in tegra_pinconf_reg()
473 		return -ENOTSUPP;  in tegra_pinconf_reg()
488 			dev_err(pmx->dev,  in tegra_pinconf_reg()
490 				param, prop, g->name);  in tegra_pinconf_reg()
492 		return -ENOTSUPP;  in tegra_pinconf_reg()
501 	dev_err(pctldev->dev, "pin_config_get op not supported\n");  in tegra_pinconf_get()
502 	return -ENOTSUPP;  in tegra_pinconf_get()
509 	dev_err(pctldev->dev, "pin_config_set op not supported\n");  in tegra_pinconf_set()
510 	return -ENOTSUPP;  in tegra_pinconf_set()
525 	g = &pmx->soc->groups[group];  in tegra_pinconf_group_get()
533 	mask = (1 << width) - 1;  in tegra_pinconf_group_get()
554 	g = &pmx->soc->groups[group];  in tegra_pinconf_group_set()
570 				dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");  in tegra_pinconf_group_set()
571 				return -EINVAL;  in tegra_pinconf_group_set()
575 		/* Special-case Boolean values; allow any non-zero as true */  in tegra_pinconf_group_set()
579 		/* Range-check user-supplied value */  in tegra_pinconf_group_set()
580 		mask = (1 << width) - 1;  in tegra_pinconf_group_set()
582 			dev_err(pctldev->dev,  in tegra_pinconf_group_set()
585 			return -EINVAL;  in tegra_pinconf_group_set()
622 	g = &pmx->soc->groups[group];  in tegra_pinconf_group_dbg_show()
632 		val &= (1 << width) - 1;  in tegra_pinconf_group_dbg_show()
638 	if (g->mux_reg >= 0) {  in tegra_pinconf_group_dbg_show()
640 		val = pmx_readl(pmx, g->mux_bank, g->mux_reg);  in tegra_pinconf_group_dbg_show()
641 		val = g->funcs[(val >> g->mux_bit) & 0x3];  in tegra_pinconf_group_dbg_show()
643 		seq_printf(s, "\n\tfunction=%s", pmx->functions[val].name);  in tegra_pinconf_group_dbg_show()
685 	for (i = 0; i < pmx->soc->ngroups; ++i) {  in tegra_pinctrl_clear_parked_bits()
686 		g = &pmx->soc->groups[i];  in tegra_pinctrl_clear_parked_bits()
687 		if (g->parked_bitmask > 0) {  in tegra_pinctrl_clear_parked_bits()
690 			if (g->mux_reg != -1) {  in tegra_pinctrl_clear_parked_bits()
691 				bank = g->mux_bank;  in tegra_pinctrl_clear_parked_bits()
692 				reg = g->mux_reg;  in tegra_pinctrl_clear_parked_bits()
694 				bank = g->drv_bank;  in tegra_pinctrl_clear_parked_bits()
695 				reg = g->drv_reg;  in tegra_pinctrl_clear_parked_bits()
699 			val &= ~g->parked_bitmask;  in tegra_pinctrl_clear_parked_bits()
719 	u32 *backup_regs = pmx->backup_regs;  in tegra_pinctrl_suspend()
724 	for (i = 0; i < pmx->nbanks; i++) {  in tegra_pinctrl_suspend()
726 		regs = pmx->regs[i];  in tegra_pinctrl_suspend()
731 	return pinctrl_force_sleep(pmx->pctl);  in tegra_pinctrl_suspend()
737 	u32 *backup_regs = pmx->backup_regs;  in tegra_pinctrl_resume()
742 	for (i = 0; i < pmx->nbanks; i++) {  in tegra_pinctrl_resume()
744 		regs = pmx->regs[i];  in tegra_pinctrl_resume()
750 	readl_relaxed(pmx->regs[0]);  in tegra_pinctrl_resume()
763 	np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible);  in tegra_pinctrl_gpio_node_has_range()
767 	has_prop = of_find_property(np, "gpio-ranges", NULL);  in tegra_pinctrl_gpio_node_has_range()
784 	pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);  in tegra_pinctrl_probe()
786 		return -ENOMEM;  in tegra_pinctrl_probe()
788 	pmx->dev = &pdev->dev;  in tegra_pinctrl_probe()
789 	pmx->soc = soc_data;  in tegra_pinctrl_probe()
793 	 * This over-allocates slightly, since not all groups are mux groups.  in tegra_pinctrl_probe()
795 	pmx->group_pins = devm_kcalloc(&pdev->dev, pmx->soc->ngroups * 4,  in tegra_pinctrl_probe()
796 				       sizeof(*pmx->group_pins), GFP_KERNEL);  in tegra_pinctrl_probe()
797 	if (!pmx->group_pins)  in tegra_pinctrl_probe()
798 		return -ENOMEM;  in tegra_pinctrl_probe()
800 	pmx->functions = devm_kcalloc(&pdev->dev, pmx->soc->nfunctions,  in tegra_pinctrl_probe()
801 				      sizeof(*pmx->functions), GFP_KERNEL);  in tegra_pinctrl_probe()
802 	if (!pmx->functions)  in tegra_pinctrl_probe()
803 		return -ENOMEM;  in tegra_pinctrl_probe()
805 	group_pins = pmx->group_pins;  in tegra_pinctrl_probe()
807 	for (fn = 0; fn < pmx->soc->nfunctions; fn++) {  in tegra_pinctrl_probe()
808 		struct tegra_function *func = &pmx->functions[fn];  in tegra_pinctrl_probe()
810 		func->name = pmx->soc->functions[fn];  in tegra_pinctrl_probe()
811 		func->groups = group_pins;  in tegra_pinctrl_probe()
813 		for (gn = 0; gn < pmx->soc->ngroups; gn++) {  in tegra_pinctrl_probe()
814 			const struct tegra_pingroup *g = &pmx->soc->groups[gn];  in tegra_pinctrl_probe()
816 			if (g->mux_reg == -1)  in tegra_pinctrl_probe()
820 				if (g->funcs[gfn] == fn)  in tegra_pinctrl_probe()
825 			BUG_ON(group_pins - pmx->group_pins >=  in tegra_pinctrl_probe()
826 				pmx->soc->ngroups * 4);  in tegra_pinctrl_probe()
827 			*group_pins++ = g->name;  in tegra_pinctrl_probe()
828 			func->ngroups++;  in tegra_pinctrl_probe()
832 	pmx->gpio_range.name = "Tegra GPIOs";  in tegra_pinctrl_probe()
833 	pmx->gpio_range.id = 0;  in tegra_pinctrl_probe()
834 	pmx->gpio_range.base = 0;  in tegra_pinctrl_probe()
835 	pmx->gpio_range.npins = pmx->soc->ngpios;  in tegra_pinctrl_probe()
837 	pmx->desc.pctlops = &tegra_pinctrl_ops;  in tegra_pinctrl_probe()
838 	pmx->desc.pmxops = &tegra_pinmux_ops;  in tegra_pinctrl_probe()
839 	pmx->desc.confops = &tegra_pinconf_ops;  in tegra_pinctrl_probe()
840 	pmx->desc.owner = THIS_MODULE;  in tegra_pinctrl_probe()
841 	pmx->desc.name = dev_name(&pdev->dev);  in tegra_pinctrl_probe()
842 	pmx->desc.pins = pmx->soc->pins;  in tegra_pinctrl_probe()
843 	pmx->desc.npins = pmx->soc->npins;  in tegra_pinctrl_probe()
851 	pmx->nbanks = i;  in tegra_pinctrl_probe()
853 	pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),  in tegra_pinctrl_probe()
855 	if (!pmx->regs)  in tegra_pinctrl_probe()
856 		return -ENOMEM;  in tegra_pinctrl_probe()
858 	pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,  in tegra_pinctrl_probe()
860 	if (!pmx->backup_regs)  in tegra_pinctrl_probe()
861 		return -ENOMEM;  in tegra_pinctrl_probe()
863 	for (i = 0; i < pmx->nbanks; i++) {  in tegra_pinctrl_probe()
864 		pmx->regs[i] = devm_platform_ioremap_resource(pdev, i);  in tegra_pinctrl_probe()
865 		if (IS_ERR(pmx->regs[i]))  in tegra_pinctrl_probe()
866 			return PTR_ERR(pmx->regs[i]);  in tegra_pinctrl_probe()
869 	pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx);  in tegra_pinctrl_probe()
870 	if (IS_ERR(pmx->pctl)) {  in tegra_pinctrl_probe()
871 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");  in tegra_pinctrl_probe()
872 		return PTR_ERR(pmx->pctl);  in tegra_pinctrl_probe()
877 	if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))  in tegra_pinctrl_probe()
878 		pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range);  in tegra_pinctrl_probe()
882 	dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");  in tegra_pinctrl_probe()