25 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
30 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
32 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
35 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
40 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
45 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
47 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
49 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
135 	return 0;  in tegra_xusb_padctl_get_group_pins()
151 #define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
159 	unsigned int i, reserve = 0, num_configs = 0;  in tegra_xusb_padctl_parse_subnode()
163 	int err = 0;  in tegra_xusb_padctl_parse_subnode()
167 	if (err < 0) {  in tegra_xusb_padctl_parse_subnode()
174 	for (i = 0; i < ARRAY_SIZE(properties); i++) {  in tegra_xusb_padctl_parse_subnode()
176 		if (err < 0) {  in tegra_xusb_padctl_parse_subnode()
187 		if (err < 0)  in tegra_xusb_padctl_parse_subnode()
198 	if (err < 0)  in tegra_xusb_padctl_parse_subnode()
205 	if (err < 0)  in tegra_xusb_padctl_parse_subnode()
213 			if (err < 0)  in tegra_xusb_padctl_parse_subnode()
222 			if (err < 0)  in tegra_xusb_padctl_parse_subnode()
227 	err = 0;  in tegra_xusb_padctl_parse_subnode()
240 	unsigned int reserved_maps = 0;  in tegra_xusb_padctl_dt_node_to_map()
243 	*num_maps = 0;  in tegra_xusb_padctl_dt_node_to_map()
250 		if (err < 0)  in tegra_xusb_padctl_dt_node_to_map()
254 	return 0;  in tegra_xusb_padctl_dt_node_to_map()
291 	return 0;  in tegra_xusb_padctl_get_function_groups()
305 	for (i = 0; i < lane->num_funcs; i++)  in tegra_xusb_padctl_pinmux_set()
317 	return 0;  in tegra_xusb_padctl_pinmux_set()
341 		/* lanes with iddq == 0 don't support this parameter */  in tegra_xusb_padctl_pinconf_group_get()
342 		if (lane->iddq == 0)  in tegra_xusb_padctl_pinconf_group_get()
348 			value = 0;  in tegra_xusb_padctl_pinconf_group_get()
361 	return 0;  in tegra_xusb_padctl_pinconf_group_get()
378 	for (i = 0; i < num_configs; i++) {  in tegra_xusb_padctl_pinconf_group_set()
384 			/* lanes with iddq == 0 don't support this parameter */  in tegra_xusb_padctl_pinconf_group_set()
385 			if (lane->iddq == 0)  in tegra_xusb_padctl_pinconf_group_set()
406 	return 0;  in tegra_xusb_padctl_pinconf_group_set()
426 	for (i = 0; i < ARRAY_SIZE(properties); i++) {  in tegra_xusb_padctl_pinconf_group_dbg_show()
430 		config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);  in tegra_xusb_padctl_pinconf_group_dbg_show()
434 		if (err < 0)  in tegra_xusb_padctl_pinconf_group_dbg_show()
457 	for (i = 0; i < ARRAY_SIZE(properties); i++) {  in tegra_xusb_padctl_pinconf_config_dbg_show()
483 	if (padctl->enable++ > 0)  in tegra_xusb_padctl_enable()
504 	return 0;  in tegra_xusb_padctl_enable()
513 	if (WARN_ON(padctl->enable == 0))  in tegra_xusb_padctl_disable()
516 	if (--padctl->enable > 0)  in tegra_xusb_padctl_disable()
537 	return 0;  in tegra_xusb_padctl_disable()
580 			err = 0;  in pcie_phy_power_on()
599 	return 0;  in pcie_phy_power_off()
640 			err = 0;  in sata_phy_power_on()
673 	return 0;  in sata_phy_power_off()
688 	unsigned int index = args->args[0];  in tegra_xusb_padctl_xlate()
690 	if (args->args_count <= 0)  in tegra_xusb_padctl_xlate()
699 #define PIN_OTG_0   0
713 	PINCTRL_PIN(PIN_OTG_0,  "otg-0"),
716 	PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
717 	PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
719 	PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
724 	PINCTRL_PIN(PIN_SATA_0, "sata-0"),
728 	"otg-0",
731 	"ulpi-0",
732 	"hsic-0",
737 	"otg-0",
740 	"ulpi-0",
741 	"hsic-0",
746 	"otg-0",
752 	"pcie-0",
760 	"pcie-0",
762 	"sata-0",
766 	"sata-0",
770 	"otg-0",
773 	"pcie-0",
778 	"sata-0",
839 	TEGRA124_LANE("otg-0",  0x004,  0, 0x3, 0, otg),
840 	TEGRA124_LANE("otg-1",  0x004,  2, 0x3, 0, otg),
841 	TEGRA124_LANE("otg-2",  0x004,  4, 0x3, 0, otg),
842 	TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
843 	TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
844 	TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
845 	TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
846 	TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
847 	TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
848 	TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
849 	TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
850 	TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
896 	padctl->regs = devm_platform_ioremap_resource(pdev, 0);  in tegra_xusb_padctl_legacy_probe()
905 	if (err < 0)  in tegra_xusb_padctl_legacy_probe()
908 	memset(&padctl->desc, 0, sizeof(padctl->desc));  in tegra_xusb_padctl_legacy_probe()
951 	return 0;  in tegra_xusb_padctl_legacy_probe()
965 	if (err < 0)  in tegra_xusb_padctl_legacy_remove()