Lines Matching +full:pctl +full:- +full:regmap
1 // SPDX-License-Identifier: GPL-2.0
21 #include <linux/regmap.h>
28 #include <linux/pinctrl/pinconf-generic.h>
35 #include "../pinctrl-utils.h"
36 #include "pinctrl-stm32.h"
114 struct regmap *regmap; member
149 return function - 1; in stm32_gpio_get_alt()
160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
169 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
170 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
176 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
177 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
183 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; in stm32_gpio_backup_speed()
184 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; in stm32_gpio_backup_speed()
190 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; in stm32_gpio_backup_bias()
191 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; in stm32_gpio_backup_bias()
204 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request() local
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); in stm32_gpio_request()
214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); in stm32_gpio_request()
216 dev_err(pctl->dev, "pin %d not in range.\n", pin); in stm32_gpio_request()
217 return -EINVAL; in stm32_gpio_request()
227 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); in stm32_gpio_get()
253 fwspec.fwnode = bank->fwnode; in stm32_gpio_to_irq()
274 ret = -EINVAL; in stm32_gpio_get_direction()
284 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_init_valid_mask() local
291 if (bank->secure_control) { in stm32_gpio_init_valid_mask()
293 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR); in stm32_gpio_init_valid_mask()
298 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i); in stm32_gpio_init_valid_mask()
321 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_irq_trigger()
325 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) in stm32_gpio_irq_trigger()
329 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); in stm32_gpio_irq_trigger()
330 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || in stm32_gpio_irq_trigger()
331 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) in stm32_gpio_irq_trigger()
343 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_set_type()
359 return -EINVAL; in stm32_gpio_set_type()
362 bank->irq_type[d->hwirq] = type; in stm32_gpio_set_type()
369 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_request_resources()
370 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_irq_request_resources() local
373 ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
377 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
379 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", in stm32_gpio_irq_request_resources()
380 irq_data->hwirq); in stm32_gpio_irq_request_resources()
389 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_release_resources()
391 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_release_resources()
417 if ((fwspec->param_count != 2) || in stm32_gpio_domain_translate()
418 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) in stm32_gpio_domain_translate()
419 return -EINVAL; in stm32_gpio_domain_translate()
421 *hwirq = fwspec->param[0]; in stm32_gpio_domain_translate()
422 *type = fwspec->param[1]; in stm32_gpio_domain_translate()
429 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_activate()
430 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_activate() local
433 if (pctl->hwlock) { in stm32_gpio_domain_activate()
434 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_gpio_domain_activate()
437 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_gpio_domain_activate()
442 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); in stm32_gpio_domain_activate()
444 if (pctl->hwlock) in stm32_gpio_domain_activate()
445 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_gpio_domain_activate()
454 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_alloc()
457 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_alloc() local
458 irq_hw_number_t hwirq = fwspec->param[0]; in stm32_gpio_domain_alloc()
466 spin_lock_irqsave(&pctl->irqmux_lock, flags); in stm32_gpio_domain_alloc()
468 if (pctl->irqmux_map & BIT(hwirq)) { in stm32_gpio_domain_alloc()
469 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq); in stm32_gpio_domain_alloc()
470 ret = -EBUSY; in stm32_gpio_domain_alloc()
472 pctl->irqmux_map |= BIT(hwirq); in stm32_gpio_domain_alloc()
475 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); in stm32_gpio_domain_alloc()
479 parent_fwspec.fwnode = d->parent->fwnode; in stm32_gpio_domain_alloc()
481 parent_fwspec.param[0] = fwspec->param[0]; in stm32_gpio_domain_alloc()
482 parent_fwspec.param[1] = fwspec->param[1]; in stm32_gpio_domain_alloc()
493 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_free()
494 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_free() local
496 unsigned long flags, hwirq = irq_data->hwirq; in stm32_gpio_domain_free()
500 spin_lock_irqsave(&pctl->irqmux_lock, flags); in stm32_gpio_domain_free()
501 pctl->irqmux_map &= ~BIT(hwirq); in stm32_gpio_domain_free()
502 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); in stm32_gpio_domain_free()
514 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) in stm32_pctrl_find_group_by_pin() argument
518 for (i = 0; i < pctl->ngroups; i++) { in stm32_pctrl_find_group_by_pin()
519 struct stm32_pinctrl_group *grp = pctl->groups + i; in stm32_pctrl_find_group_by_pin()
521 if (grp->pin == pin) in stm32_pctrl_find_group_by_pin()
528 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, in stm32_pctrl_is_function_valid() argument
533 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_is_function_valid()
534 const struct stm32_desc_pin *pin = pctl->pins + i; in stm32_pctrl_is_function_valid()
535 const struct stm32_desc_function *func = pin->functions; in stm32_pctrl_is_function_valid()
537 if (pin->pin.number != pin_num) in stm32_pctrl_is_function_valid()
541 if (func->num == fnum) in stm32_pctrl_is_function_valid()
549 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num); in stm32_pctrl_is_function_valid()
554 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, in stm32_pctrl_dt_node_to_map_func() argument
560 return -ENOSPC; in stm32_pctrl_dt_node_to_map_func()
563 (*map)[*num_maps].data.mux.group = grp->name; in stm32_pctrl_dt_node_to_map_func()
565 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) in stm32_pctrl_dt_node_to_map_func()
566 return -EINVAL; in stm32_pctrl_dt_node_to_map_func()
580 struct stm32_pinctrl *pctl; in stm32_pctrl_dt_subnode_to_map() local
590 pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_dt_subnode_to_map()
594 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", in stm32_pctrl_dt_subnode_to_map()
596 return -EINVAL; in stm32_pctrl_dt_subnode_to_map()
607 num_pins = pins->length / sizeof(u32); in stm32_pctrl_dt_subnode_to_map()
616 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
636 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { in stm32_pctrl_dt_subnode_to_map()
637 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
641 grp = stm32_pctrl_find_group_by_pin(pctl, pin); in stm32_pctrl_dt_subnode_to_map()
643 dev_err(pctl->dev, "unable to match pin %d to group\n", in stm32_pctrl_dt_subnode_to_map()
645 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
649 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, in stm32_pctrl_dt_subnode_to_map()
656 reserved_maps, num_maps, grp->name, in stm32_pctrl_dt_subnode_to_map()
694 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_get_groups_count() local
696 return pctl->ngroups; in stm32_pctrl_get_groups_count()
702 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_get_group_name() local
704 return pctl->groups[group].name; in stm32_pctrl_get_group_name()
712 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_get_group_pins() local
714 *pins = (unsigned *)&pctl->groups[group].pin; in stm32_pctrl_get_group_pins()
747 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pmx_get_func_groups() local
749 *groups = pctl->grp_names; in stm32_pmx_get_func_groups()
750 *num_groups = pctl->ngroups; in stm32_pmx_get_func_groups()
758 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pmx_set_mode() local
765 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_set_mode()
767 if (pctl->hwlock) { in stm32_pmx_set_mode()
768 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pmx_set_mode()
771 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pmx_set_mode()
776 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_set_mode()
779 writel_relaxed(val, bank->base + alt_offset); in stm32_pmx_set_mode()
781 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
784 writel_relaxed(val, bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
786 if (pctl->hwlock) in stm32_pmx_set_mode()
787 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pmx_set_mode()
792 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_set_mode()
805 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_get_mode()
807 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_get_mode()
811 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_get_mode()
815 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_get_mode()
823 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pmx_set_mux() local
824 struct stm32_pinctrl_group *g = pctl->groups + group; in stm32_pmx_set_mux()
830 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); in stm32_pmx_set_mux()
832 return -EINVAL; in stm32_pmx_set_mux()
834 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); in stm32_pmx_set_mux()
836 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pmx_set_mux()
837 return -EINVAL; in stm32_pmx_set_mux()
840 bank = gpiochip_get_data(range->gc); in stm32_pmx_set_mux()
841 pin = stm32_gpio_pin(g->pin); in stm32_pmx_set_mux()
853 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); in stm32_pmx_gpio_set_direction()
861 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pmx_request() local
866 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pmx_request()
867 return -EINVAL; in stm32_pmx_request()
870 if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) { in stm32_pmx_request()
871 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio); in stm32_pmx_request()
872 return -EACCES; in stm32_pmx_request()
893 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_driving() local
898 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_driving()
900 if (pctl->hwlock) { in stm32_pconf_set_driving()
901 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_driving()
904 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_driving()
909 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
912 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
914 if (pctl->hwlock) in stm32_pconf_set_driving()
915 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_driving()
920 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_driving()
931 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_driving()
933 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_get_driving()
936 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_driving()
944 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_speed() local
949 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_speed()
951 if (pctl->hwlock) { in stm32_pconf_set_speed()
952 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_speed()
955 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_speed()
960 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
963 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
965 if (pctl->hwlock) in stm32_pconf_set_speed()
966 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_speed()
971 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_speed()
982 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_speed()
984 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_get_speed()
987 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_speed()
995 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_bias() local
1000 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_bias()
1002 if (pctl->hwlock) { in stm32_pconf_set_bias()
1003 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_bias()
1006 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_bias()
1011 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1014 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1016 if (pctl->hwlock) in stm32_pconf_set_bias()
1017 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_bias()
1022 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_bias()
1033 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_bias()
1035 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_get_bias()
1038 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_bias()
1049 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get()
1052 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & in stm32_pconf_get()
1055 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & in stm32_pconf_get()
1058 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get()
1067 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_parse_conf() local
1074 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pconf_parse_conf()
1075 return -EINVAL; in stm32_pconf_parse_conf()
1078 bank = gpiochip_get_data(range->gc); in stm32_pconf_parse_conf()
1081 if (!gpiochip_line_is_valid(range->gc, offset)) { in stm32_pconf_parse_conf()
1082 dev_warn(pctl->dev, "Can't access gpio %d\n", pin); in stm32_pconf_parse_conf()
1083 return -EACCES; in stm32_pconf_parse_conf()
1110 ret = -ENOTSUPP; in stm32_pconf_parse_conf()
1120 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_group_get() local
1122 *config = pctl->groups[group].config; in stm32_pconf_group_get()
1130 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_group_set() local
1131 struct stm32_pinctrl_group *g = &pctl->groups[group]; in stm32_pconf_group_set()
1135 mutex_lock(&pctldev->mutex); in stm32_pconf_group_set()
1136 ret = stm32_pconf_parse_conf(pctldev, g->pin, in stm32_pconf_group_set()
1139 mutex_unlock(&pctldev->mutex); in stm32_pconf_group_set()
1143 g->config = configs[i]; in stm32_pconf_group_set()
1166 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl, in stm32_pconf_get_pin_desc_by_pin_number() argument
1169 struct stm32_desc_pin *pins = pctl->pins; in stm32_pconf_get_pin_desc_by_pin_number()
1172 for (i = 0; i < pctl->npins; i++) { in stm32_pconf_get_pin_desc_by_pin_number()
1173 if (pins->pin.number == pin_number) in stm32_pconf_get_pin_desc_by_pin_number()
1184 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_dbg_show() local
1202 bank = gpiochip_get_data(range->gc); in stm32_pconf_dbg_show()
1205 if (!gpiochip_line_is_valid(range->gc, offset)) { in stm32_pconf_dbg_show()
1219 seq_printf(s, "- %s - %s", in stm32_pconf_dbg_show()
1229 seq_printf(s, "- %s - %s - %s - %s %s", in stm32_pconf_dbg_show()
1240 pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin); in stm32_pconf_dbg_show()
1244 seq_printf(s, "%d (%s) - %s - %s - %s %s", alt, in stm32_pconf_dbg_show()
1245 pin_desc->functions[alt + 1].name, in stm32_pconf_dbg_show()
1264 static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl, in stm32_pctrl_get_desc_pin_from_gpio() argument
1268 unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset; in stm32_pctrl_get_desc_pin_from_gpio()
1273 if (stm32_pin_nb < pctl->npins) { in stm32_pctrl_get_desc_pin_from_gpio()
1274 pin_desc = pctl->pins + stm32_pin_nb; in stm32_pctrl_get_desc_pin_from_gpio()
1275 if (pin_desc->pin.number == stm32_pin_nb) in stm32_pctrl_get_desc_pin_from_gpio()
1280 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_get_desc_pin_from_gpio()
1281 pin_desc = pctl->pins + i; in stm32_pctrl_get_desc_pin_from_gpio()
1282 if (pin_desc->pin.number == stm32_pin_nb) in stm32_pctrl_get_desc_pin_from_gpio()
1288 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode) in stm32_gpiolib_register_bank() argument
1290 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; in stm32_gpiolib_register_bank()
1292 struct pinctrl_gpio_range *range = &bank->range; in stm32_gpiolib_register_bank()
1294 struct device *dev = pctl->dev; in stm32_gpiolib_register_bank()
1301 if (!IS_ERR(bank->rstc)) in stm32_gpiolib_register_bank()
1302 reset_control_deassert(bank->rstc); in stm32_gpiolib_register_bank()
1305 return -ENODEV; in stm32_gpiolib_register_bank()
1307 bank->base = devm_ioremap_resource(dev, &res); in stm32_gpiolib_register_bank()
1308 if (IS_ERR(bank->base)) in stm32_gpiolib_register_bank()
1309 return PTR_ERR(bank->base); in stm32_gpiolib_register_bank()
1311 err = clk_prepare_enable(bank->clk); in stm32_gpiolib_register_bank()
1317 bank->gpio_chip = stm32_gpio_template; in stm32_gpiolib_register_bank()
1319 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1321 if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) { in stm32_gpiolib_register_bank()
1323 bank->gpio_chip.base = args.args[1]; in stm32_gpiolib_register_bank()
1327 while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args)) in stm32_gpiolib_register_bank()
1330 bank_nr = pctl->nbanks; in stm32_gpiolib_register_bank()
1331 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1332 range->name = bank->gpio_chip.label; in stm32_gpiolib_register_bank()
1333 range->id = bank_nr; in stm32_gpiolib_register_bank()
1334 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1335 range->base = range->id * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1336 range->npins = npins; in stm32_gpiolib_register_bank()
1337 range->gc = &bank->gpio_chip; in stm32_gpiolib_register_bank()
1338 pinctrl_add_gpio_range(pctl->pctl_dev, in stm32_gpiolib_register_bank()
1339 &pctl->banks[bank_nr].range); in stm32_gpiolib_register_bank()
1342 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr)) in stm32_gpiolib_register_bank()
1345 bank->gpio_chip.base = -1; in stm32_gpiolib_register_bank()
1347 bank->gpio_chip.ngpio = npins; in stm32_gpiolib_register_bank()
1348 bank->gpio_chip.fwnode = fwnode; in stm32_gpiolib_register_bank()
1349 bank->gpio_chip.parent = dev; in stm32_gpiolib_register_bank()
1350 bank->bank_nr = bank_nr; in stm32_gpiolib_register_bank()
1351 bank->bank_ioport_nr = bank_ioport_nr; in stm32_gpiolib_register_bank()
1352 bank->secure_control = pctl->match_data->secure_control; in stm32_gpiolib_register_bank()
1353 spin_lock_init(&bank->lock); in stm32_gpiolib_register_bank()
1355 if (pctl->domain) { in stm32_gpiolib_register_bank()
1357 bank->fwnode = fwnode; in stm32_gpiolib_register_bank()
1359 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, in stm32_gpiolib_register_bank()
1360 bank->fwnode, &stm32_gpio_domain_ops, in stm32_gpiolib_register_bank()
1363 if (!bank->domain) { in stm32_gpiolib_register_bank()
1364 err = -ENODEV; in stm32_gpiolib_register_bank()
1371 err = -ENOMEM; in stm32_gpiolib_register_bank()
1376 stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i); in stm32_gpiolib_register_bank()
1377 if (stm32_pin && stm32_pin->pin.name) { in stm32_gpiolib_register_bank()
1378 names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name); in stm32_gpiolib_register_bank()
1380 err = -ENOMEM; in stm32_gpiolib_register_bank()
1388 bank->gpio_chip.names = (const char * const *)names; in stm32_gpiolib_register_bank()
1390 err = gpiochip_add_data(&bank->gpio_chip, bank); in stm32_gpiolib_register_bank()
1396 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1400 clk_disable_unprepare(bank->clk); in stm32_gpiolib_register_bank()
1406 struct device_node *np = pdev->dev.of_node; in stm32_pctrl_get_irq_domain()
1410 if (!of_property_present(np, "interrupt-parent")) in stm32_pctrl_get_irq_domain()
1415 return ERR_PTR(-ENXIO); in stm32_pctrl_get_irq_domain()
1421 return ERR_PTR(-EPROBE_DEFER); in stm32_pctrl_get_irq_domain()
1427 struct stm32_pinctrl *pctl) in stm32_pctrl_dt_setup_irq() argument
1429 struct device_node *np = pdev->dev.of_node; in stm32_pctrl_dt_setup_irq()
1430 struct device *dev = &pdev->dev; in stm32_pctrl_dt_setup_irq()
1431 struct regmap *rm; in stm32_pctrl_dt_setup_irq()
1435 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in stm32_pctrl_dt_setup_irq()
1436 if (IS_ERR(pctl->regmap)) in stm32_pctrl_dt_setup_irq()
1437 return PTR_ERR(pctl->regmap); in stm32_pctrl_dt_setup_irq()
1439 rm = pctl->regmap; in stm32_pctrl_dt_setup_irq()
1456 mux.msb = mux.lsb + mask_width - 1; in stm32_pctrl_dt_setup_irq()
1461 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); in stm32_pctrl_dt_setup_irq()
1462 if (IS_ERR(pctl->irqmux[i])) in stm32_pctrl_dt_setup_irq()
1463 return PTR_ERR(pctl->irqmux[i]); in stm32_pctrl_dt_setup_irq()
1471 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); in stm32_pctrl_build_state() local
1474 pctl->ngroups = pctl->npins; in stm32_pctrl_build_state()
1477 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1478 sizeof(*pctl->groups), GFP_KERNEL); in stm32_pctrl_build_state()
1479 if (!pctl->groups) in stm32_pctrl_build_state()
1480 return -ENOMEM; in stm32_pctrl_build_state()
1483 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1484 sizeof(*pctl->grp_names), GFP_KERNEL); in stm32_pctrl_build_state()
1485 if (!pctl->grp_names) in stm32_pctrl_build_state()
1486 return -ENOMEM; in stm32_pctrl_build_state()
1488 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_build_state()
1489 const struct stm32_desc_pin *pin = pctl->pins + i; in stm32_pctrl_build_state()
1490 struct stm32_pinctrl_group *group = pctl->groups + i; in stm32_pctrl_build_state()
1492 group->name = pin->pin.name; in stm32_pctrl_build_state()
1493 group->pin = pin->pin.number; in stm32_pctrl_build_state()
1494 pctl->grp_names[i] = pin->pin.name; in stm32_pctrl_build_state()
1500 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, in stm32_pctrl_create_pins_tab() argument
1506 for (i = 0; i < pctl->match_data->npins; i++) { in stm32_pctrl_create_pins_tab()
1507 p = pctl->match_data->pins + i; in stm32_pctrl_create_pins_tab()
1508 if (pctl->pkg && !(pctl->pkg & p->pkg)) in stm32_pctrl_create_pins_tab()
1510 pins->pin = p->pin; in stm32_pctrl_create_pins_tab()
1511 memcpy((struct stm32_desc_pin *)pins->functions, p->functions, in stm32_pctrl_create_pins_tab()
1517 pctl->npins = nb_pins_available; in stm32_pctrl_create_pins_tab()
1526 struct device *dev = &pdev->dev; in stm32_pctl_probe()
1527 struct stm32_pinctrl *pctl; in stm32_pctl_probe() local
1534 return -EINVAL; in stm32_pctl_probe()
1536 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); in stm32_pctl_probe()
1537 if (!pctl) in stm32_pctl_probe()
1538 return -ENOMEM; in stm32_pctl_probe()
1540 platform_set_drvdata(pdev, pctl); in stm32_pctl_probe()
1543 pctl->domain = stm32_pctrl_get_irq_domain(pdev); in stm32_pctl_probe()
1544 if (IS_ERR(pctl->domain)) in stm32_pctl_probe()
1545 return PTR_ERR(pctl->domain); in stm32_pctl_probe()
1546 if (!pctl->domain) in stm32_pctl_probe()
1550 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); in stm32_pctl_probe()
1552 if (hwlock_id == -EPROBE_DEFER) in stm32_pctl_probe()
1555 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); in stm32_pctl_probe()
1558 spin_lock_init(&pctl->irqmux_lock); in stm32_pctl_probe()
1560 pctl->dev = dev; in stm32_pctl_probe()
1561 pctl->match_data = match_data; in stm32_pctl_probe()
1564 if (!device_property_read_u32(dev, "st,package", &pctl->pkg)) in stm32_pctl_probe()
1565 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); in stm32_pctl_probe()
1567 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, in stm32_pctl_probe()
1568 sizeof(*pctl->pins), GFP_KERNEL); in stm32_pctl_probe()
1569 if (!pctl->pins) in stm32_pctl_probe()
1570 return -ENOMEM; in stm32_pctl_probe()
1572 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); in stm32_pctl_probe()
1579 return -EINVAL; in stm32_pctl_probe()
1582 if (pctl->domain) { in stm32_pctl_probe()
1583 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); in stm32_pctl_probe()
1588 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), in stm32_pctl_probe()
1591 return -ENOMEM; in stm32_pctl_probe()
1593 for (i = 0; i < pctl->npins; i++) in stm32_pctl_probe()
1594 pins[i] = pctl->pins[i].pin; in stm32_pctl_probe()
1596 pctl->pctl_desc.name = dev_name(&pdev->dev); in stm32_pctl_probe()
1597 pctl->pctl_desc.owner = THIS_MODULE; in stm32_pctl_probe()
1598 pctl->pctl_desc.pins = pins; in stm32_pctl_probe()
1599 pctl->pctl_desc.npins = pctl->npins; in stm32_pctl_probe()
1600 pctl->pctl_desc.link_consumers = true; in stm32_pctl_probe()
1601 pctl->pctl_desc.confops = &stm32_pconf_ops; in stm32_pctl_probe()
1602 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; in stm32_pctl_probe()
1603 pctl->pctl_desc.pmxops = &stm32_pmx_ops; in stm32_pctl_probe()
1604 pctl->dev = &pdev->dev; in stm32_pctl_probe()
1606 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, in stm32_pctl_probe()
1607 pctl); in stm32_pctl_probe()
1609 if (IS_ERR(pctl->pctl_dev)) { in stm32_pctl_probe()
1610 dev_err(&pdev->dev, "Failed pinctrl registration\n"); in stm32_pctl_probe()
1611 return PTR_ERR(pctl->pctl_dev); in stm32_pctl_probe()
1617 return -EINVAL; in stm32_pctl_probe()
1619 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), in stm32_pctl_probe()
1621 if (!pctl->banks) in stm32_pctl_probe()
1622 return -ENOMEM; in stm32_pctl_probe()
1626 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe()
1629 bank->rstc = of_reset_control_get_exclusive(np, NULL); in stm32_pctl_probe()
1630 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) { in stm32_pctl_probe()
1632 return -EPROBE_DEFER; in stm32_pctl_probe()
1635 bank->clk = of_clk_get_by_name(np, NULL); in stm32_pctl_probe()
1636 if (IS_ERR(bank->clk)) { in stm32_pctl_probe()
1638 return dev_err_probe(dev, PTR_ERR(bank->clk), in stm32_pctl_probe()
1645 ret = stm32_gpiolib_register_bank(pctl, child); in stm32_pctl_probe()
1649 for (i = 0; i < pctl->nbanks; i++) in stm32_pctl_probe()
1650 clk_disable_unprepare(pctl->banks[i].clk); in stm32_pctl_probe()
1655 pctl->nbanks++; in stm32_pctl_probe()
1664 struct stm32_pinctrl *pctl, u32 pin) in stm32_pinctrl_restore_gpio_regs() argument
1666 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); in stm32_pinctrl_restore_gpio_regs()
1673 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); in stm32_pinctrl_restore_gpio_regs()
1677 if (!gpiochip_line_is_valid(range->gc, offset)) in stm32_pinctrl_restore_gpio_regs()
1680 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); in stm32_pinctrl_restore_gpio_regs()
1682 if (!desc || (!pin_is_irq && !desc->gpio_owner)) in stm32_pinctrl_restore_gpio_regs()
1685 bank = gpiochip_get_data(range->gc); in stm32_pinctrl_restore_gpio_regs()
1687 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; in stm32_pinctrl_restore_gpio_regs()
1689 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; in stm32_pinctrl_restore_gpio_regs()
1697 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); in stm32_pinctrl_restore_gpio_regs()
1702 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); in stm32_pinctrl_restore_gpio_regs()
1708 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; in stm32_pinctrl_restore_gpio_regs()
1714 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; in stm32_pinctrl_restore_gpio_regs()
1721 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); in stm32_pinctrl_restore_gpio_regs()
1728 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); in stm32_pinctrl_suspend() local
1731 for (i = 0; i < pctl->nbanks; i++) in stm32_pinctrl_suspend()
1732 clk_disable(pctl->banks[i].clk); in stm32_pinctrl_suspend()
1739 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); in stm32_pinctrl_resume() local
1740 struct stm32_pinctrl_group *g = pctl->groups; in stm32_pinctrl_resume()
1743 for (i = 0; i < pctl->nbanks; i++) in stm32_pinctrl_resume()
1744 clk_enable(pctl->banks[i].clk); in stm32_pinctrl_resume()
1746 for (i = 0; i < pctl->ngroups; i++, g++) in stm32_pinctrl_resume()
1747 stm32_pinctrl_restore_gpio_regs(pctl, g->pin); in stm32_pinctrl_resume()