Lines Matching +full:dout +full:- +full:default
1 // SPDX-License-Identifier: GPL-2.0
27 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
30 #include "../pinctrl-utils.h"
33 #include "pinctrl-starfive-jh7110.h"
52 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
53 * | din | dout | doen | function | pin |
100 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_pin_dbg_show()
102 seq_printf(s, "%s", dev_name(pctldev->dev)); in jh7110_pin_dbg_show()
104 if (pin < sfp->gc.ngpio) { in jh7110_pin_dbg_show()
107 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset); in jh7110_pin_dbg_show() local
108 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); in jh7110_pin_dbg_show()
109 u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset); in jh7110_pin_dbg_show()
111 dout = (dout >> shift) & info->dout_mask; in jh7110_pin_dbg_show()
112 doen = (doen >> shift) & info->doen_mask; in jh7110_pin_dbg_show()
113 gpi = ((gpi >> shift) - 2) & info->gpi_mask; in jh7110_pin_dbg_show()
115 seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi); in jh7110_pin_dbg_show()
128 struct device *dev = sfp->gc.parent; in jh7110_dt_node_to_map()
144 return -ENOMEM; in jh7110_dt_node_to_map()
148 return -ENOMEM; in jh7110_dt_node_to_map()
152 mutex_lock(&sfp->mutex); in jh7110_dt_node_to_map()
163 ret = -EINVAL; in jh7110_dt_node_to_map()
169 ret = -ENOMEM; in jh7110_dt_node_to_map()
177 ret = -ENOMEM; in jh7110_dt_node_to_map()
183 ret = -ENOMEM; in jh7110_dt_node_to_map()
195 map[nmaps].data.mux.function = np->name; in jh7110_dt_node_to_map()
224 ret = pinmux_generic_add_function(pctldev, np->name, in jh7110_dt_node_to_map()
227 dev_err(dev, "error adding function %s: %d\n", np->name, ret); in jh7110_dt_node_to_map()
230 mutex_unlock(&sfp->mutex); in jh7110_dt_node_to_map()
238 mutex_unlock(&sfp->mutex); in jh7110_dt_node_to_map()
252 unsigned int din, u32 dout, u32 doen) in jh7110_set_gpiomux() argument
254 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_set_gpiomux()
258 u32 dout_mask = info->dout_mask << shift; in jh7110_set_gpiomux()
259 u32 done_mask = info->doen_mask << shift; in jh7110_set_gpiomux()
266 reg_dout = sfp->base + info->dout_reg_base + offset; in jh7110_set_gpiomux()
267 reg_doen = sfp->base + info->doen_reg_base + offset; in jh7110_set_gpiomux()
268 dout <<= shift; in jh7110_set_gpiomux()
274 reg_din = sfp->base + info->gpi_reg_base + ioffset; in jh7110_set_gpiomux()
276 imask = info->gpi_mask << ishift; in jh7110_set_gpiomux()
281 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_set_gpiomux()
282 dout |= readl_relaxed(reg_dout) & ~dout_mask; in jh7110_set_gpiomux()
283 writel_relaxed(dout, reg_dout); in jh7110_set_gpiomux()
290 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_set_gpiomux()
298 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_set_mux()
305 return -EINVAL; in jh7110_set_mux()
307 pinmux = group->data; in jh7110_set_mux()
308 for (i = 0; i < group->grp.npins; i++) { in jh7110_set_mux()
311 if (info->jh7110_set_one_pin_mux) in jh7110_set_mux()
312 info->jh7110_set_one_pin_mux(sfp, in jh7110_set_mux()
352 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_padcfg_rmw()
357 if (!info->jh7110_get_padcfg_base) in jh7110_padcfg_rmw()
360 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin); in jh7110_padcfg_rmw()
364 reg = sfp->base + padcfg_base + 4 * pin; in jh7110_padcfg_rmw()
367 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_padcfg_rmw()
370 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_padcfg_rmw()
377 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_pinconf_get()
383 if (!info->jh7110_get_padcfg_base) in jh7110_pinconf_get()
386 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin); in jh7110_pinconf_get()
390 padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin); in jh7110_pinconf_get()
420 default: in jh7110_pinconf_get()
421 return -ENOTSUPP; in jh7110_pinconf_get()
425 return enabled ? 0 : -EINVAL; in jh7110_pinconf_get()
436 return -EINVAL; in jh7110_pinconf_group_get()
438 return jh7110_pinconf_get(pctldev, group->grp.pins[0], config); in jh7110_pinconf_group_get()
453 return -EINVAL; in jh7110_pinconf_group_set()
468 return -ENOTSUPP; in jh7110_pinconf_group_set()
474 return -ENOTSUPP; in jh7110_pinconf_group_set()
504 default: in jh7110_pinconf_group_set()
505 return -ENOTSUPP; in jh7110_pinconf_group_set()
509 for (i = 0; i < group->grp.npins; i++) in jh7110_pinconf_group_set()
510 jh7110_padcfg_rmw(sfp, group->grp.pins[i], mask, value); in jh7110_pinconf_group_set()
520 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_pinconf_dbg_show()
524 if (!info->jh7110_get_padcfg_base) in jh7110_pinconf_dbg_show()
527 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin); in jh7110_pinconf_dbg_show()
531 value = readl_relaxed(sfp->base + padcfg_base + 4 * pin); in jh7110_pinconf_dbg_show()
551 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_gpio_get_direction()
554 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); in jh7110_gpio_get_direction()
556 doen = (doen >> shift) & info->doen_mask; in jh7110_gpio_get_direction()
567 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_gpio_direction_input()
574 if (info->jh7110_set_one_pin_mux) in jh7110_gpio_direction_input()
575 info->jh7110_set_one_pin_mux(sfp, gpio, in jh7110_gpio_direction_input()
586 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_gpio_direction_output()
588 if (info->jh7110_set_one_pin_mux) in jh7110_gpio_direction_output()
589 info->jh7110_set_one_pin_mux(sfp, gpio, in jh7110_gpio_direction_output()
604 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_gpio_get()
605 void __iomem *reg = sfp->base + info->gpioin_reg_base in jh7110_gpio_get()
616 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_gpio_set()
619 void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset; in jh7110_gpio_set()
620 u32 dout = (value ? GPOUT_HIGH : GPOUT_LOW) << shift; in jh7110_gpio_set() local
621 u32 mask = info->dout_mask << shift; in jh7110_gpio_set()
624 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_gpio_set()
625 dout |= readl_relaxed(reg_dout) & ~mask; in jh7110_gpio_set()
626 writel_relaxed(dout, reg_dout); in jh7110_gpio_set()
627 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_gpio_set()
646 return -ENOTSUPP; in jh7110_gpio_set_config()
652 return -ENOTSUPP; in jh7110_gpio_set_config()
666 default: in jh7110_gpio_set_config()
667 return -ENOTSUPP; in jh7110_gpio_set_config()
679 sfp->gpios.name = sfp->gc.label; in jh7110_gpio_add_pin_ranges()
680 sfp->gpios.base = sfp->gc.base; in jh7110_gpio_add_pin_ranges()
681 sfp->gpios.pin_base = 0; in jh7110_gpio_add_pin_ranges()
682 sfp->gpios.npins = sfp->gc.ngpio; in jh7110_gpio_add_pin_ranges()
683 sfp->gpios.gc = &sfp->gc; in jh7110_gpio_add_pin_ranges()
684 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios); in jh7110_gpio_add_pin_ranges()
691 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; in jh7110_irq_ack()
693 void __iomem *ic = sfp->base + irq_reg->ic_reg_base in jh7110_irq_ack()
699 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_irq_ack()
703 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_irq_ack()
709 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; in jh7110_irq_mask()
711 void __iomem *ie = sfp->base + irq_reg->ie_reg_base in jh7110_irq_mask()
717 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_irq_mask()
720 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_irq_mask()
722 gpiochip_disable_irq(&sfp->gc, d->hwirq); in jh7110_irq_mask()
728 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; in jh7110_irq_mask_ack()
730 void __iomem *ie = sfp->base + irq_reg->ie_reg_base in jh7110_irq_mask_ack()
732 void __iomem *ic = sfp->base + irq_reg->ic_reg_base in jh7110_irq_mask_ack()
738 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_irq_mask_ack()
745 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_irq_mask_ack()
751 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; in jh7110_irq_unmask()
753 void __iomem *ie = sfp->base + irq_reg->ie_reg_base in jh7110_irq_unmask()
759 gpiochip_enable_irq(&sfp->gc, d->hwirq); in jh7110_irq_unmask()
761 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_irq_unmask()
764 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_irq_unmask()
770 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg; in jh7110_irq_set_type()
772 void __iomem *base = sfp->base + 4 * (gpio / 32); in jh7110_irq_set_type()
803 default: in jh7110_irq_set_type()
804 return -EINVAL; in jh7110_irq_set_type()
812 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_irq_set_type()
813 irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask; in jh7110_irq_set_type()
814 writel_relaxed(irq_type, base + irq_reg->is_reg_base); in jh7110_irq_set_type()
816 edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask; in jh7110_irq_set_type()
817 writel_relaxed(edge_both, base + irq_reg->ibe_reg_base); in jh7110_irq_set_type()
819 polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask; in jh7110_irq_set_type()
820 writel_relaxed(polarity, base + irq_reg->iev_reg_base); in jh7110_irq_set_type()
821 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_irq_set_type()
842 struct device *dev = &pdev->dev; in jh7110_pinctrl_probe()
850 info = of_device_get_match_data(&pdev->dev); in jh7110_pinctrl_probe()
852 return -ENODEV; in jh7110_pinctrl_probe()
854 if (!info->pins || !info->npins) { in jh7110_pinctrl_probe()
856 return -EINVAL; in jh7110_pinctrl_probe()
861 return -ENOMEM; in jh7110_pinctrl_probe()
864 sfp->saved_regs = devm_kcalloc(dev, info->nsaved_regs, in jh7110_pinctrl_probe()
865 sizeof(*sfp->saved_regs), GFP_KERNEL); in jh7110_pinctrl_probe()
866 if (!sfp->saved_regs) in jh7110_pinctrl_probe()
867 return -ENOMEM; in jh7110_pinctrl_probe()
870 sfp->base = devm_platform_ioremap_resource(pdev, 0); in jh7110_pinctrl_probe()
871 if (IS_ERR(sfp->base)) in jh7110_pinctrl_probe()
872 return PTR_ERR(sfp->base); in jh7110_pinctrl_probe()
901 jh7110_pinctrl_desc = devm_kzalloc(&pdev->dev, in jh7110_pinctrl_probe()
905 return -ENOMEM; in jh7110_pinctrl_probe()
907 jh7110_pinctrl_desc->name = dev_name(dev); in jh7110_pinctrl_probe()
908 jh7110_pinctrl_desc->pins = info->pins; in jh7110_pinctrl_probe()
909 jh7110_pinctrl_desc->npins = info->npins; in jh7110_pinctrl_probe()
910 jh7110_pinctrl_desc->pctlops = &jh7110_pinctrl_ops; in jh7110_pinctrl_probe()
911 jh7110_pinctrl_desc->pmxops = &jh7110_pinmux_ops; in jh7110_pinctrl_probe()
912 jh7110_pinctrl_desc->confops = &jh7110_pinconf_ops; in jh7110_pinctrl_probe()
913 jh7110_pinctrl_desc->owner = THIS_MODULE; in jh7110_pinctrl_probe()
915 sfp->info = info; in jh7110_pinctrl_probe()
916 sfp->dev = dev; in jh7110_pinctrl_probe()
918 sfp->gc.parent = dev; in jh7110_pinctrl_probe()
919 raw_spin_lock_init(&sfp->lock); in jh7110_pinctrl_probe()
920 mutex_init(&sfp->mutex); in jh7110_pinctrl_probe()
924 sfp, &sfp->pctl); in jh7110_pinctrl_probe()
929 sfp->gc.label = dev_name(dev); in jh7110_pinctrl_probe()
930 sfp->gc.owner = THIS_MODULE; in jh7110_pinctrl_probe()
931 sfp->gc.request = pinctrl_gpio_request; in jh7110_pinctrl_probe()
932 sfp->gc.free = pinctrl_gpio_free; in jh7110_pinctrl_probe()
933 sfp->gc.get_direction = jh7110_gpio_get_direction; in jh7110_pinctrl_probe()
934 sfp->gc.direction_input = jh7110_gpio_direction_input; in jh7110_pinctrl_probe()
935 sfp->gc.direction_output = jh7110_gpio_direction_output; in jh7110_pinctrl_probe()
936 sfp->gc.get = jh7110_gpio_get; in jh7110_pinctrl_probe()
937 sfp->gc.set = jh7110_gpio_set; in jh7110_pinctrl_probe()
938 sfp->gc.set_config = jh7110_gpio_set_config; in jh7110_pinctrl_probe()
939 sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges; in jh7110_pinctrl_probe()
940 sfp->gc.base = info->gc_base; in jh7110_pinctrl_probe()
941 sfp->gc.ngpio = info->ngpios; in jh7110_pinctrl_probe()
943 jh7110_irq_chip.name = sfp->gc.label; in jh7110_pinctrl_probe()
944 gpio_irq_chip_set_chip(&sfp->gc.irq, &jh7110_irq_chip); in jh7110_pinctrl_probe()
945 sfp->gc.irq.parent_handler = info->jh7110_gpio_irq_handler; in jh7110_pinctrl_probe()
946 sfp->gc.irq.num_parents = 1; in jh7110_pinctrl_probe()
947 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents, in jh7110_pinctrl_probe()
948 sizeof(*sfp->gc.irq.parents), in jh7110_pinctrl_probe()
950 if (!sfp->gc.irq.parents) in jh7110_pinctrl_probe()
951 return -ENOMEM; in jh7110_pinctrl_probe()
952 sfp->gc.irq.default_type = IRQ_TYPE_NONE; in jh7110_pinctrl_probe()
953 sfp->gc.irq.handler = handle_bad_irq; in jh7110_pinctrl_probe()
954 sfp->gc.irq.init_hw = info->jh7110_gpio_init_hw; in jh7110_pinctrl_probe()
959 sfp->gc.irq.parents[0] = ret; in jh7110_pinctrl_probe()
961 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp); in jh7110_pinctrl_probe()
965 dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio); in jh7110_pinctrl_probe()
967 return pinctrl_enable(sfp->pctl); in jh7110_pinctrl_probe()
977 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_pinctrl_suspend()
978 for (i = 0 ; i < sfp->info->nsaved_regs ; i++) in jh7110_pinctrl_suspend()
979 sfp->saved_regs[i] = readl_relaxed(sfp->base + 4 * i); in jh7110_pinctrl_suspend()
981 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_pinctrl_suspend()
991 raw_spin_lock_irqsave(&sfp->lock, flags); in jh7110_pinctrl_resume()
992 for (i = 0 ; i < sfp->info->nsaved_regs ; i++) in jh7110_pinctrl_resume()
993 writel_relaxed(sfp->saved_regs[i], sfp->base + 4 * i); in jh7110_pinctrl_resume()
995 raw_spin_unlock_irqrestore(&sfp->lock, flags); in jh7110_pinctrl_resume()