Lines Matching +full:gpio +full:- +full:pin +full:- +full:ic
1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl / GPIO driver for StarFive JH7100 SoC
11 #include <linux/gpio/driver.h>
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
36 * Refer to Section 12. GPIO Registers in the JH7100 data sheet:
37 * https://github.com/starfive-tech/JH7100_Docs
42 * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts
43 * are enabled. If set to 0 the GPIO interrupts are disabled.
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
55 * interrupt is level-triggered.
60 * Edge-Trigger Interrupt Type. If set to 1 the interrupt gets triggered on
68 * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
69 * interrupt is triggered on a falling edge (edge-triggered) or low level
70 * (level-triggered).
82 * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
88 * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
99 * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is
100 * a digital 1 and if 0 the pin is a digital 0.
105 * From the data sheet section 12.2, there are 64 32-bit output data registers
107 * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is
109 * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n
123 * Pad Control Bits. There are 16 pad control bits for each pin located in 103
124 * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
144 * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
151 * sfp->gpio.pin_base = PAD_INVALID_GPIO then
152 * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number.
160 * | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 |
161 * | dout | doen | din | dout rev | doen rev | gpio nr |
165 * | 31 | 30 - 8 | 7 - 0 |
170 return v & (NR_GPIOS - 1); in starfive_pinmux_to_gpio()
175 return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0)); in starfive_pinmux_to_dout()
180 return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0)); in starfive_pinmux_to_doen()
189 * The maximum GPIO output current depends on the chosen drive strength:
203 return (clamp(i, 14U, 63U) - 14) / 7; in starfive_drive_strength_from_max_mA()
217 unsigned int pin) in starfive_pin_to_gpio() argument
219 return pin - sfp->gpios.pin_base; in starfive_pin_to_gpio()
223 unsigned int gpio) in starfive_gpio_to_pin() argument
225 return sfp->gpios.pin_base + gpio; in starfive_gpio_to_pin()
243 PINCTRL_PIN(PAD_GPIO(0), "GPIO[0]"),
244 PINCTRL_PIN(PAD_GPIO(1), "GPIO[1]"),
245 PINCTRL_PIN(PAD_GPIO(2), "GPIO[2]"),
246 PINCTRL_PIN(PAD_GPIO(3), "GPIO[3]"),
247 PINCTRL_PIN(PAD_GPIO(4), "GPIO[4]"),
248 PINCTRL_PIN(PAD_GPIO(5), "GPIO[5]"),
249 PINCTRL_PIN(PAD_GPIO(6), "GPIO[6]"),
250 PINCTRL_PIN(PAD_GPIO(7), "GPIO[7]"),
251 PINCTRL_PIN(PAD_GPIO(8), "GPIO[8]"),
252 PINCTRL_PIN(PAD_GPIO(9), "GPIO[9]"),
253 PINCTRL_PIN(PAD_GPIO(10), "GPIO[10]"),
254 PINCTRL_PIN(PAD_GPIO(11), "GPIO[11]"),
255 PINCTRL_PIN(PAD_GPIO(12), "GPIO[12]"),
256 PINCTRL_PIN(PAD_GPIO(13), "GPIO[13]"),
257 PINCTRL_PIN(PAD_GPIO(14), "GPIO[14]"),
258 PINCTRL_PIN(PAD_GPIO(15), "GPIO[15]"),
259 PINCTRL_PIN(PAD_GPIO(16), "GPIO[16]"),
260 PINCTRL_PIN(PAD_GPIO(17), "GPIO[17]"),
261 PINCTRL_PIN(PAD_GPIO(18), "GPIO[18]"),
262 PINCTRL_PIN(PAD_GPIO(19), "GPIO[19]"),
263 PINCTRL_PIN(PAD_GPIO(20), "GPIO[20]"),
264 PINCTRL_PIN(PAD_GPIO(21), "GPIO[21]"),
265 PINCTRL_PIN(PAD_GPIO(22), "GPIO[22]"),
266 PINCTRL_PIN(PAD_GPIO(23), "GPIO[23]"),
267 PINCTRL_PIN(PAD_GPIO(24), "GPIO[24]"),
268 PINCTRL_PIN(PAD_GPIO(25), "GPIO[25]"),
269 PINCTRL_PIN(PAD_GPIO(26), "GPIO[26]"),
270 PINCTRL_PIN(PAD_GPIO(27), "GPIO[27]"),
271 PINCTRL_PIN(PAD_GPIO(28), "GPIO[28]"),
272 PINCTRL_PIN(PAD_GPIO(29), "GPIO[29]"),
273 PINCTRL_PIN(PAD_GPIO(30), "GPIO[30]"),
274 PINCTRL_PIN(PAD_GPIO(31), "GPIO[31]"),
275 PINCTRL_PIN(PAD_GPIO(32), "GPIO[32]"),
276 PINCTRL_PIN(PAD_GPIO(33), "GPIO[33]"),
277 PINCTRL_PIN(PAD_GPIO(34), "GPIO[34]"),
278 PINCTRL_PIN(PAD_GPIO(35), "GPIO[35]"),
279 PINCTRL_PIN(PAD_GPIO(36), "GPIO[36]"),
280 PINCTRL_PIN(PAD_GPIO(37), "GPIO[37]"),
281 PINCTRL_PIN(PAD_GPIO(38), "GPIO[38]"),
282 PINCTRL_PIN(PAD_GPIO(39), "GPIO[39]"),
283 PINCTRL_PIN(PAD_GPIO(40), "GPIO[40]"),
284 PINCTRL_PIN(PAD_GPIO(41), "GPIO[41]"),
285 PINCTRL_PIN(PAD_GPIO(42), "GPIO[42]"),
286 PINCTRL_PIN(PAD_GPIO(43), "GPIO[43]"),
287 PINCTRL_PIN(PAD_GPIO(44), "GPIO[44]"),
288 PINCTRL_PIN(PAD_GPIO(45), "GPIO[45]"),
289 PINCTRL_PIN(PAD_GPIO(46), "GPIO[46]"),
290 PINCTRL_PIN(PAD_GPIO(47), "GPIO[47]"),
291 PINCTRL_PIN(PAD_GPIO(48), "GPIO[48]"),
292 PINCTRL_PIN(PAD_GPIO(49), "GPIO[49]"),
293 PINCTRL_PIN(PAD_GPIO(50), "GPIO[50]"),
294 PINCTRL_PIN(PAD_GPIO(51), "GPIO[51]"),
295 PINCTRL_PIN(PAD_GPIO(52), "GPIO[52]"),
296 PINCTRL_PIN(PAD_GPIO(53), "GPIO[53]"),
297 PINCTRL_PIN(PAD_GPIO(54), "GPIO[54]"),
298 PINCTRL_PIN(PAD_GPIO(55), "GPIO[55]"),
299 PINCTRL_PIN(PAD_GPIO(56), "GPIO[56]"),
300 PINCTRL_PIN(PAD_GPIO(57), "GPIO[57]"),
301 PINCTRL_PIN(PAD_GPIO(58), "GPIO[58]"),
302 PINCTRL_PIN(PAD_GPIO(59), "GPIO[59]"),
303 PINCTRL_PIN(PAD_GPIO(60), "GPIO[60]"),
304 PINCTRL_PIN(PAD_GPIO(61), "GPIO[61]"),
305 PINCTRL_PIN(PAD_GPIO(62), "GPIO[62]"),
306 PINCTRL_PIN(PAD_GPIO(63), "GPIO[63]"),
454 unsigned int pin) in starfive_pin_dbg_show() argument
457 unsigned int gpio = starfive_pin_to_gpio(sfp, pin); in starfive_pin_dbg_show() local
461 if (gpio >= NR_GPIOS) in starfive_pin_dbg_show()
464 reg = sfp->base + GPON_DOUT_CFG + 8 * gpio; in starfive_pin_dbg_show()
482 struct device *dev = sfp->gc.parent; in starfive_dt_node_to_map()
501 return -EINVAL; in starfive_dt_node_to_map()
506 return -EINVAL; in starfive_dt_node_to_map()
518 return -ENOMEM; in starfive_dt_node_to_map()
522 return -ENOMEM; in starfive_dt_node_to_map()
526 mutex_lock(&sfp->mutex); in starfive_dt_node_to_map()
533 ret = -ENOMEM; in starfive_dt_node_to_map()
542 ret = -ENOMEM; in starfive_dt_node_to_map()
548 ret = -ENOMEM; in starfive_dt_node_to_map()
557 unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]); in starfive_dt_node_to_map() local
559 pins[i] = starfive_gpio_to_pin(sfp, gpio); in starfive_dt_node_to_map()
563 map[nmaps].data.mux.function = np->name; in starfive_dt_node_to_map()
569 ret = -ENOMEM; in starfive_dt_node_to_map()
584 ret = -EINVAL; in starfive_dt_node_to_map()
598 dev_err(dev, "error parsing pin config of group %s: %d\n", in starfive_dt_node_to_map()
612 ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL); in starfive_dt_node_to_map()
614 dev_err(dev, "error adding function %s: %d\n", np->name, ret); in starfive_dt_node_to_map()
620 mutex_unlock(&sfp->mutex); in starfive_dt_node_to_map()
625 mutex_unlock(&sfp->mutex); in starfive_dt_node_to_map()
642 struct device *dev = sfp->gc.parent; in starfive_set_mux()
649 return -EINVAL; in starfive_set_mux()
651 pinmux = group->data; in starfive_set_mux()
652 for (i = 0; i < group->grp.npins; i++) { in starfive_set_mux()
654 unsigned int gpio = starfive_pinmux_to_gpio(v); in starfive_set_mux() local
663 dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n", in starfive_set_mux()
664 gpio, dout, doen, din); in starfive_set_mux()
666 reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio; in starfive_set_mux()
667 reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; in starfive_set_mux()
669 reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din; in starfive_set_mux()
673 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_set_mux()
677 writel_relaxed(gpio + 2, reg_din); in starfive_set_mux()
678 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_set_mux()
693 unsigned int pin) in starfive_padctl_get() argument
695 void __iomem *reg = sfp->padctl + 4 * (pin / 2); in starfive_padctl_get()
696 int shift = 16 * (pin % 2); in starfive_padctl_get()
702 unsigned int pin, in starfive_padctl_rmw() argument
705 void __iomem *reg = sfp->padctl + 4 * (pin / 2); in starfive_padctl_rmw()
706 int shift = 16 * (pin % 2); in starfive_padctl_rmw()
711 dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value); in starfive_padctl_rmw()
713 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_padctl_rmw()
716 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_padctl_rmw()
722 { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },
727 PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),
737 unsigned int pin, unsigned long *config) in starfive_pinconf_get() argument
741 u16 value = starfive_padctl_get(sfp, pin); in starfive_pinconf_get()
779 return -ENOTSUPP; in starfive_pinconf_get()
783 return enabled ? 0 : -EINVAL; in starfive_pinconf_get()
793 return -EINVAL; in starfive_pinconf_group_get()
795 return starfive_pinconf_get(pctldev, group->grp.pins[0], config); in starfive_pinconf_group_get()
810 return -EINVAL; in starfive_pinconf_group_set()
825 return -ENOTSUPP; in starfive_pinconf_group_set()
831 return -ENOTSUPP; in starfive_pinconf_group_set()
870 return -ENOTSUPP; in starfive_pinconf_group_set()
874 for (i = 0; i < group->grp.npins; i++) in starfive_pinconf_group_set()
875 starfive_padctl_rmw(sfp, group->grp.pins[i], mask, value); in starfive_pinconf_group_set()
882 struct seq_file *s, unsigned int pin) in starfive_pinconf_dbg_show() argument
885 u16 value = starfive_padctl_get(sfp, pin); in starfive_pinconf_dbg_show()
914 static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) in starfive_gpio_get_direction() argument
917 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; in starfive_gpio_get_direction()
926 unsigned int gpio) in starfive_gpio_direction_input() argument
929 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; in starfive_gpio_direction_input()
933 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), in starfive_gpio_direction_input()
937 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_gpio_direction_input()
939 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_gpio_direction_input()
944 unsigned int gpio, int value) in starfive_gpio_direction_output() argument
947 void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio; in starfive_gpio_direction_output()
948 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; in starfive_gpio_direction_output()
951 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_gpio_direction_output()
954 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_gpio_direction_output()
957 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), in starfive_gpio_direction_output()
964 static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio) in starfive_gpio_get() argument
967 void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32); in starfive_gpio_get()
969 return !!(readl_relaxed(din) & BIT(gpio % 32)); in starfive_gpio_get()
972 static int starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio, in starfive_gpio_set() argument
976 void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio; in starfive_gpio_set()
979 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_gpio_set()
981 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_gpio_set()
986 static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio, in starfive_gpio_set_config() argument
1001 return -ENOTSUPP; in starfive_gpio_set_config()
1007 return -ENOTSUPP; in starfive_gpio_set_config()
1022 return -ENOTSUPP; in starfive_gpio_set_config()
1025 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value); in starfive_gpio_set_config()
1033 sfp->gpios.name = sfp->gc.label; in starfive_gpio_add_pin_ranges()
1034 sfp->gpios.base = sfp->gc.base; in starfive_gpio_add_pin_ranges()
1036 * sfp->gpios.pin_base depends on the chosen signal group in starfive_gpio_add_pin_ranges()
1039 sfp->gpios.npins = NR_GPIOS; in starfive_gpio_add_pin_ranges()
1040 sfp->gpios.gc = &sfp->gc; in starfive_gpio_add_pin_ranges()
1041 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios); in starfive_gpio_add_pin_ranges()
1048 irq_hw_number_t gpio = irqd_to_hwirq(d); in starfive_irq_ack() local
1049 void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32); in starfive_irq_ack() local
1050 u32 mask = BIT(gpio % 32); in starfive_irq_ack()
1053 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_irq_ack()
1054 writel_relaxed(mask, ic); in starfive_irq_ack()
1055 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_irq_ack()
1061 irq_hw_number_t gpio = irqd_to_hwirq(d); in starfive_irq_mask() local
1062 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32); in starfive_irq_mask()
1063 u32 mask = BIT(gpio % 32); in starfive_irq_mask()
1067 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_irq_mask()
1070 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_irq_mask()
1072 gpiochip_disable_irq(&sfp->gc, gpio); in starfive_irq_mask()
1078 irq_hw_number_t gpio = irqd_to_hwirq(d); in starfive_irq_mask_ack() local
1079 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32); in starfive_irq_mask_ack()
1080 void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32); in starfive_irq_mask_ack() local
1081 u32 mask = BIT(gpio % 32); in starfive_irq_mask_ack()
1085 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_irq_mask_ack()
1088 writel_relaxed(mask, ic); in starfive_irq_mask_ack()
1089 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_irq_mask_ack()
1095 irq_hw_number_t gpio = irqd_to_hwirq(d); in starfive_irq_unmask() local
1096 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32); in starfive_irq_unmask()
1097 u32 mask = BIT(gpio % 32); in starfive_irq_unmask()
1101 gpiochip_enable_irq(&sfp->gc, gpio); in starfive_irq_unmask()
1103 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_irq_unmask()
1106 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_irq_unmask()
1112 irq_hw_number_t gpio = irqd_to_hwirq(d); in starfive_irq_set_type() local
1113 void __iomem *base = sfp->base + 4 * (gpio / 32); in starfive_irq_set_type()
1114 u32 mask = BIT(gpio % 32); in starfive_irq_set_type()
1145 return -EINVAL; in starfive_irq_set_type()
1153 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_irq_set_type()
1160 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_irq_set_type()
1165 .name = "StarFive GPIO",
1180 unsigned int pin; in starfive_gpio_irq_handler() local
1184 mis = readl_relaxed(sfp->base + GPIOMIS + 0); in starfive_gpio_irq_handler()
1185 for_each_set_bit(pin, &mis, 32) in starfive_gpio_irq_handler()
1186 generic_handle_domain_irq(sfp->gc.irq.domain, pin); in starfive_gpio_irq_handler()
1188 mis = readl_relaxed(sfp->base + GPIOMIS + 4); in starfive_gpio_irq_handler()
1189 for_each_set_bit(pin, &mis, 32) in starfive_gpio_irq_handler()
1190 generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32); in starfive_gpio_irq_handler()
1199 /* mask all GPIO interrupts */ in starfive_gpio_init_hw()
1200 writel(0, sfp->base + GPIOIE + 0); in starfive_gpio_init_hw()
1201 writel(0, sfp->base + GPIOIE + 4); in starfive_gpio_init_hw()
1203 writel(~0U, sfp->base + GPIOIC + 0); in starfive_gpio_init_hw()
1204 writel(~0U, sfp->base + GPIOIC + 4); in starfive_gpio_init_hw()
1205 /* enable GPIO interrupts */ in starfive_gpio_init_hw()
1206 writel(1, sfp->base + GPIOEN); in starfive_gpio_init_hw()
1217 struct device *dev = &pdev->dev; in starfive_probe()
1226 return -ENOMEM; in starfive_probe()
1228 sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); in starfive_probe()
1229 if (IS_ERR(sfp->base)) in starfive_probe()
1230 return PTR_ERR(sfp->base); in starfive_probe()
1232 sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl"); in starfive_probe()
1233 if (IS_ERR(sfp->padctl)) in starfive_probe()
1234 return PTR_ERR(sfp->padctl); in starfive_probe()
1253 * We don't want to assert reset and risk undoing pin muxing for the in starfive_probe()
1262 sfp->gc.parent = dev; in starfive_probe()
1263 raw_spin_lock_init(&sfp->lock); in starfive_probe()
1264 mutex_init(&sfp->mutex); in starfive_probe()
1266 ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl); in starfive_probe()
1270 if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) { in starfive_probe()
1272 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value); in starfive_probe()
1273 writel(value, sfp->padctl + IO_PADSHARE_SEL); in starfive_probe()
1276 value = readl(sfp->padctl + IO_PADSHARE_SEL); in starfive_probe()
1279 sfp->gpios.pin_base = PAD_INVALID_GPIO; in starfive_probe()
1282 sfp->gpios.pin_base = PAD_GPIO(0); in starfive_probe()
1285 sfp->gpios.pin_base = PAD_FUNC_SHARE(72); in starfive_probe()
1288 sfp->gpios.pin_base = PAD_FUNC_SHARE(70); in starfive_probe()
1291 sfp->gpios.pin_base = PAD_FUNC_SHARE(0); in starfive_probe()
1294 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value); in starfive_probe()
1297 sfp->gc.label = dev_name(dev); in starfive_probe()
1298 sfp->gc.owner = THIS_MODULE; in starfive_probe()
1299 sfp->gc.request = pinctrl_gpio_request; in starfive_probe()
1300 sfp->gc.free = pinctrl_gpio_free; in starfive_probe()
1301 sfp->gc.get_direction = starfive_gpio_get_direction; in starfive_probe()
1302 sfp->gc.direction_input = starfive_gpio_direction_input; in starfive_probe()
1303 sfp->gc.direction_output = starfive_gpio_direction_output; in starfive_probe()
1304 sfp->gc.get = starfive_gpio_get; in starfive_probe()
1305 sfp->gc.set = starfive_gpio_set; in starfive_probe()
1306 sfp->gc.set_config = starfive_gpio_set_config; in starfive_probe()
1307 sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges; in starfive_probe()
1308 sfp->gc.base = -1; in starfive_probe()
1309 sfp->gc.ngpio = NR_GPIOS; in starfive_probe()
1311 gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip); in starfive_probe()
1312 sfp->gc.irq.parent_handler = starfive_gpio_irq_handler; in starfive_probe()
1313 sfp->gc.irq.num_parents = 1; in starfive_probe()
1314 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents, in starfive_probe()
1315 sizeof(*sfp->gc.irq.parents), GFP_KERNEL); in starfive_probe()
1316 if (!sfp->gc.irq.parents) in starfive_probe()
1317 return -ENOMEM; in starfive_probe()
1318 sfp->gc.irq.default_type = IRQ_TYPE_NONE; in starfive_probe()
1319 sfp->gc.irq.handler = handle_bad_irq; in starfive_probe()
1320 sfp->gc.irq.init_hw = starfive_gpio_init_hw; in starfive_probe()
1325 sfp->gc.irq.parents[0] = ret; in starfive_probe()
1327 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp); in starfive_probe()
1331 irq_domain_set_pm_device(sfp->gc.irq.domain, dev); in starfive_probe()
1334 return pinctrl_enable(sfp->pctl); in starfive_probe()
1338 { .compatible = "starfive,jh7100-pinctrl" },