Lines Matching +full:dout +full:- +full:default
1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37 * https://github.com/starfive-tech/JH7100_Docs
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
55 * interrupt is level-triggered.
60 * Edge-Trigger Interrupt Type. If set to 1 the interrupt gets triggered on
68 * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
69 * interrupt is triggered on a falling edge (edge-triggered) or low level
70 * (level-triggered).
82 * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
88 * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
105 * From the data sheet section 12.2, there are 64 32-bit output data registers
124 * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
144 * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
151 * sfp->gpio.pin_base = PAD_INVALID_GPIO then
160 * | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 |
161 * | dout | doen | din | dout rev | doen rev | gpio nr |
165 * | 31 | 30 - 8 | 7 - 0 |
166 * | dout/doen rev | unused | dout/doen |
170 return v & (NR_GPIOS - 1); in starfive_pinmux_to_gpio()
175 return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0)); in starfive_pinmux_to_dout()
180 return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0)); in starfive_pinmux_to_doen()
203 return (clamp(i, 14U, 63U) - 14) / 7; in starfive_drive_strength_from_max_mA()
219 return pin - sfp->gpios.pin_base; in starfive_pin_to_gpio()
225 return sfp->gpios.pin_base + gpio; in starfive_gpio_to_pin()
459 u32 dout, doen; in starfive_pin_dbg_show() local
464 reg = sfp->base + GPON_DOUT_CFG + 8 * gpio; in starfive_pin_dbg_show()
465 dout = readl_relaxed(reg + 0x000); in starfive_pin_dbg_show()
468 seq_printf(s, "dout=%lu%s doen=%lu%s", in starfive_pin_dbg_show()
469 dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "", in starfive_pin_dbg_show()
482 struct device *dev = sfp->gc.parent; in starfive_dt_node_to_map()
501 return -EINVAL; in starfive_dt_node_to_map()
506 return -EINVAL; in starfive_dt_node_to_map()
518 return -ENOMEM; in starfive_dt_node_to_map()
522 return -ENOMEM; in starfive_dt_node_to_map()
526 mutex_lock(&sfp->mutex); in starfive_dt_node_to_map()
533 ret = -ENOMEM; in starfive_dt_node_to_map()
542 ret = -ENOMEM; in starfive_dt_node_to_map()
548 ret = -ENOMEM; in starfive_dt_node_to_map()
563 map[nmaps].data.mux.function = np->name; in starfive_dt_node_to_map()
569 ret = -ENOMEM; in starfive_dt_node_to_map()
584 ret = -EINVAL; in starfive_dt_node_to_map()
612 ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL); in starfive_dt_node_to_map()
614 dev_err(dev, "error adding function %s: %d\n", np->name, ret); in starfive_dt_node_to_map()
620 mutex_unlock(&sfp->mutex); in starfive_dt_node_to_map()
625 mutex_unlock(&sfp->mutex); in starfive_dt_node_to_map()
642 struct device *dev = sfp->gc.parent; in starfive_set_mux()
649 return -EINVAL; in starfive_set_mux()
651 pinmux = group->data; in starfive_set_mux()
652 for (i = 0; i < group->grp.npins; i++) { in starfive_set_mux()
655 u32 dout = starfive_pinmux_to_dout(v); in starfive_set_mux() local
663 dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n", in starfive_set_mux()
664 gpio, dout, doen, din); in starfive_set_mux()
666 reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio; in starfive_set_mux()
667 reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; in starfive_set_mux()
669 reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din; in starfive_set_mux()
673 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_set_mux()
674 writel_relaxed(dout, reg_dout); in starfive_set_mux()
678 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_set_mux()
695 void __iomem *reg = sfp->padctl + 4 * (pin / 2); in starfive_padctl_get()
705 void __iomem *reg = sfp->padctl + 4 * (pin / 2); in starfive_padctl_rmw()
711 dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value); in starfive_padctl_rmw()
713 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_padctl_rmw()
716 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_padctl_rmw()
722 { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },
727 PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),
778 default: in starfive_pinconf_get()
779 return -ENOTSUPP; in starfive_pinconf_get()
783 return enabled ? 0 : -EINVAL; in starfive_pinconf_get()
793 return -EINVAL; in starfive_pinconf_group_get()
795 return starfive_pinconf_get(pctldev, group->grp.pins[0], config); in starfive_pinconf_group_get()
810 return -EINVAL; in starfive_pinconf_group_set()
825 return -ENOTSUPP; in starfive_pinconf_group_set()
831 return -ENOTSUPP; in starfive_pinconf_group_set()
869 default: in starfive_pinconf_group_set()
870 return -ENOTSUPP; in starfive_pinconf_group_set()
874 for (i = 0; i < group->grp.npins; i++) in starfive_pinconf_group_set()
875 starfive_padctl_rmw(sfp, group->grp.pins[i], mask, value); in starfive_pinconf_group_set()
917 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; in starfive_gpio_get_direction()
929 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; in starfive_gpio_direction_input()
937 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_gpio_direction_input()
939 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_gpio_direction_input()
947 void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio; in starfive_gpio_direction_output() local
948 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; in starfive_gpio_direction_output()
951 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_gpio_direction_output()
952 writel_relaxed(value, dout); in starfive_gpio_direction_output()
954 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_gpio_direction_output()
967 void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32); in starfive_gpio_get()
976 void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio; in starfive_gpio_set() local
979 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_gpio_set()
980 writel_relaxed(value, dout); in starfive_gpio_set()
981 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_gpio_set()
999 return -ENOTSUPP; in starfive_gpio_set_config()
1005 return -ENOTSUPP; in starfive_gpio_set_config()
1019 default: in starfive_gpio_set_config()
1020 return -ENOTSUPP; in starfive_gpio_set_config()
1031 sfp->gpios.name = sfp->gc.label; in starfive_gpio_add_pin_ranges()
1032 sfp->gpios.base = sfp->gc.base; in starfive_gpio_add_pin_ranges()
1034 * sfp->gpios.pin_base depends on the chosen signal group in starfive_gpio_add_pin_ranges()
1037 sfp->gpios.npins = NR_GPIOS; in starfive_gpio_add_pin_ranges()
1038 sfp->gpios.gc = &sfp->gc; in starfive_gpio_add_pin_ranges()
1039 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios); in starfive_gpio_add_pin_ranges()
1047 void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32); in starfive_irq_ack()
1051 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_irq_ack()
1053 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_irq_ack()
1060 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32); in starfive_irq_mask()
1065 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_irq_mask()
1068 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_irq_mask()
1070 gpiochip_disable_irq(&sfp->gc, gpio); in starfive_irq_mask()
1077 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32); in starfive_irq_mask_ack()
1078 void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32); in starfive_irq_mask_ack()
1083 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_irq_mask_ack()
1087 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_irq_mask_ack()
1094 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32); in starfive_irq_unmask()
1099 gpiochip_enable_irq(&sfp->gc, gpio); in starfive_irq_unmask()
1101 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_irq_unmask()
1104 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_irq_unmask()
1111 void __iomem *base = sfp->base + 4 * (gpio / 32); in starfive_irq_set_type()
1142 default: in starfive_irq_set_type()
1143 return -EINVAL; in starfive_irq_set_type()
1151 raw_spin_lock_irqsave(&sfp->lock, flags); in starfive_irq_set_type()
1158 raw_spin_unlock_irqrestore(&sfp->lock, flags); in starfive_irq_set_type()
1182 mis = readl_relaxed(sfp->base + GPIOMIS + 0); in starfive_gpio_irq_handler()
1184 generic_handle_domain_irq(sfp->gc.irq.domain, pin); in starfive_gpio_irq_handler()
1186 mis = readl_relaxed(sfp->base + GPIOMIS + 4); in starfive_gpio_irq_handler()
1188 generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32); in starfive_gpio_irq_handler()
1198 writel(0, sfp->base + GPIOIE + 0); in starfive_gpio_init_hw()
1199 writel(0, sfp->base + GPIOIE + 4); in starfive_gpio_init_hw()
1201 writel(~0U, sfp->base + GPIOIC + 0); in starfive_gpio_init_hw()
1202 writel(~0U, sfp->base + GPIOIC + 4); in starfive_gpio_init_hw()
1204 writel(1, sfp->base + GPIOEN); in starfive_gpio_init_hw()
1215 struct device *dev = &pdev->dev; in starfive_probe()
1224 return -ENOMEM; in starfive_probe()
1226 sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); in starfive_probe()
1227 if (IS_ERR(sfp->base)) in starfive_probe()
1228 return PTR_ERR(sfp->base); in starfive_probe()
1230 sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl"); in starfive_probe()
1231 if (IS_ERR(sfp->padctl)) in starfive_probe()
1232 return PTR_ERR(sfp->padctl); in starfive_probe()
1260 sfp->gc.parent = dev; in starfive_probe()
1261 raw_spin_lock_init(&sfp->lock); in starfive_probe()
1262 mutex_init(&sfp->mutex); in starfive_probe()
1264 ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl); in starfive_probe()
1268 if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) { in starfive_probe()
1270 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value); in starfive_probe()
1271 writel(value, sfp->padctl + IO_PADSHARE_SEL); in starfive_probe()
1274 value = readl(sfp->padctl + IO_PADSHARE_SEL); in starfive_probe()
1277 sfp->gpios.pin_base = PAD_INVALID_GPIO; in starfive_probe()
1280 sfp->gpios.pin_base = PAD_GPIO(0); in starfive_probe()
1283 sfp->gpios.pin_base = PAD_FUNC_SHARE(72); in starfive_probe()
1286 sfp->gpios.pin_base = PAD_FUNC_SHARE(70); in starfive_probe()
1289 sfp->gpios.pin_base = PAD_FUNC_SHARE(0); in starfive_probe()
1291 default: in starfive_probe()
1292 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value); in starfive_probe()
1295 sfp->gc.label = dev_name(dev); in starfive_probe()
1296 sfp->gc.owner = THIS_MODULE; in starfive_probe()
1297 sfp->gc.request = pinctrl_gpio_request; in starfive_probe()
1298 sfp->gc.free = pinctrl_gpio_free; in starfive_probe()
1299 sfp->gc.get_direction = starfive_gpio_get_direction; in starfive_probe()
1300 sfp->gc.direction_input = starfive_gpio_direction_input; in starfive_probe()
1301 sfp->gc.direction_output = starfive_gpio_direction_output; in starfive_probe()
1302 sfp->gc.get = starfive_gpio_get; in starfive_probe()
1303 sfp->gc.set = starfive_gpio_set; in starfive_probe()
1304 sfp->gc.set_config = starfive_gpio_set_config; in starfive_probe()
1305 sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges; in starfive_probe()
1306 sfp->gc.base = -1; in starfive_probe()
1307 sfp->gc.ngpio = NR_GPIOS; in starfive_probe()
1309 gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip); in starfive_probe()
1310 sfp->gc.irq.parent_handler = starfive_gpio_irq_handler; in starfive_probe()
1311 sfp->gc.irq.num_parents = 1; in starfive_probe()
1312 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents, in starfive_probe()
1313 sizeof(*sfp->gc.irq.parents), GFP_KERNEL); in starfive_probe()
1314 if (!sfp->gc.irq.parents) in starfive_probe()
1315 return -ENOMEM; in starfive_probe()
1316 sfp->gc.irq.default_type = IRQ_TYPE_NONE; in starfive_probe()
1317 sfp->gc.irq.handler = handle_bad_irq; in starfive_probe()
1318 sfp->gc.irq.init_hw = starfive_gpio_init_hw; in starfive_probe()
1323 sfp->gc.irq.parents[0] = ret; in starfive_probe()
1325 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp); in starfive_probe()
1329 irq_domain_set_pm_device(sfp->gc.irq.domain, dev); in starfive_probe()
1332 return pinctrl_enable(sfp->pctl); in starfive_probe()
1336 { .compatible = "starfive,jh7100-pinctrl" },