Lines Matching +full:wakeup +full:- +full:interrupt +full:- +full:controller

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25  * enum pincfg_type - possible pin configuration types supported.
46  * packed together into a 16-bits. The upper 8-bits represent the configuration
47  * type and the lower 8-bits hold the value of the configuration type.
70  * enum pud_index - Possible index values to access the pud_val array.
84  * enum eint_type - possible external interrupt types.
87  * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
88  * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
90  * Samsung GPIO controller groups all the available pins into banks. The pins
91  * in a pin bank can support external gpio interrupts or external wakeup
93  * difference between external gpio and external wakeup interrupts is that
94  * the wakeup interrupts can additionally wakeup the system if it is in
104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
135  * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
137  * @pctl_offset: starting offset of the pin-bank registers.
138  * @pctl_res_idx: index of base address for pin-bank registers.
141  * @eint_type: type of the external interrupt supported by the bank.
143  * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
145  * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.
146  * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
147  * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
148  * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
169  * struct samsung_pin_bank: represent a controller pin-bank.
171  * @pctl_base: base address of the pin-bank registers
172  * @pctl_offset: starting offset of the pin-bank registers.
174  * @eint_base: base address of the pin-bank EINT registers.
176  * @eint_type: type of the external interrupt supported by the bank.
178  * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
180  * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.
181  * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
182  * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
183  * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
187  * @soc_priv: per-bank private data for SoC-specific code.
189  * @drvdata: link to controller driver data
193  * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
229  * struct samsung_retention_data: runtime pin-bank retention control data.
249  * struct samsung_retention_data: represent a pin-bank retention control data.
266  * struct samsung_pin_ctrl: represent a pin controller.
267  * @pin_banks: list of pin banks included in this controller.
272  *	interrupts for the controller.
273  * @eint_wkup_init: platform specific callback to setup the external wakeup
274  *	interrupts for the controller.
275  * @suspend: platform specific suspend callback, executed during pin controller
277  * @resume: platform specific resume callback, executed during pin controller
280  * External wakeup interrupts must define at least eint_wkup_init,
299  * @virt_base: register base address of the controller; this will be equal
300  *             to each bank samsung_pin_bank->pctl_base and used on legacy
303  * @dev: device instance representing the controller.
304  * @irq: interrpt number used by the controller to notify gpio interrupts.
306  * @ctrl: pin controller instance managed by the driver.
307  * @pctl: pin controller descriptor registered with the pinctrl subsystem.
313  * @nr_pins: number of pins supported by the controller.
315  * @suspend: platform specific suspend callback, executed during pin controller
317  * @resume: platform specific resume callback, executed during pin controller
348  * @ctrl: array of pin controller data.