316 static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask)  in s3c64xx_gpio_irq_set_mask()  argument
318 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);  in s3c64xx_gpio_irq_set_mask()
320 	unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;  in s3c64xx_gpio_irq_set_mask()
332 static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd)  in s3c64xx_gpio_irq_unmask()  argument
334 	s3c64xx_gpio_irq_set_mask(irqd, false);  in s3c64xx_gpio_irq_unmask()
337 static void s3c64xx_gpio_irq_mask(struct irq_data *irqd)  in s3c64xx_gpio_irq_mask()  argument
339 	s3c64xx_gpio_irq_set_mask(irqd, true);  in s3c64xx_gpio_irq_mask()
342 static void s3c64xx_gpio_irq_ack(struct irq_data *irqd)  in s3c64xx_gpio_irq_ack()  argument
344 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);  in s3c64xx_gpio_irq_ack()
346 	unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;  in s3c64xx_gpio_irq_ack()
352 static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)  in s3c64xx_gpio_irq_set_type()  argument
354 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);  in s3c64xx_gpio_irq_set_type()
367 	s3c64xx_irq_set_handler(irqd, type);  in s3c64xx_gpio_irq_set_type()
371 	shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;  in s3c64xx_gpio_irq_set_type()
379 	s3c64xx_irq_set_function(d, bank, irqd->hwirq);  in s3c64xx_gpio_irq_set_type()
521 static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask)  in s3c64xx_eint0_irq_set_mask()  argument
524 					irq_data_get_irq_chip_data(irqd);  in s3c64xx_eint0_irq_set_mask()
530 		val |= 1 << ddata->eints[irqd->hwirq];  in s3c64xx_eint0_irq_set_mask()
532 		val &= ~(1 << ddata->eints[irqd->hwirq]);  in s3c64xx_eint0_irq_set_mask()
536 static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd)  in s3c64xx_eint0_irq_unmask()  argument
538 	s3c64xx_eint0_irq_set_mask(irqd, false);  in s3c64xx_eint0_irq_unmask()
541 static void s3c64xx_eint0_irq_mask(struct irq_data *irqd)  in s3c64xx_eint0_irq_mask()  argument
543 	s3c64xx_eint0_irq_set_mask(irqd, true);  in s3c64xx_eint0_irq_mask()
546 static void s3c64xx_eint0_irq_ack(struct irq_data *irqd)  in s3c64xx_eint0_irq_ack()  argument
549 					irq_data_get_irq_chip_data(irqd);  in s3c64xx_eint0_irq_ack()
552 	writel(1 << ddata->eints[irqd->hwirq],  in s3c64xx_eint0_irq_ack()
556 static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)  in s3c64xx_eint0_irq_set_type()  argument
559 					irq_data_get_irq_chip_data(irqd);  in s3c64xx_eint0_irq_set_type()
573 	s3c64xx_irq_set_handler(irqd, type);  in s3c64xx_eint0_irq_set_type()
577 	shift = ddata->eints[irqd->hwirq];  in s3c64xx_eint0_irq_set_type()
589 	s3c64xx_irq_set_function(d, bank, irqd->hwirq);  in s3c64xx_eint0_irq_set_type()