Lines Matching refs:PIN_CFG_PUPD
49 #define PIN_CFG_PUPD BIT(4) macro
70 PIN_CFG_PUPD | \
390 RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
393 RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
396 RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
399 RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
401 RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
403 RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
405 RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
407 RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
409 RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
411 RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
413 RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
415 RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
419 RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
421 RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
423 RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
425 RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
427 RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1283 if (!(cfg & PIN_CFG_PUPD)) in rzg2l_pinctrl_pinconf_get()
1422 if (!(cfg & PIN_CFG_PUPD)) in rzg2l_pinctrl_pinconf_set()
1874 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1877 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1879 RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
2086 PIN_CFG_PUPD | PIN_CFG_NOD)) },
2088 PIN_CFG_PUPD | PIN_CFG_NOD)) },
2090 PIN_CFG_PUPD)) },
2092 PIN_CFG_PUPD)) },
2094 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2096 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2098 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2100 PIN_CFG_PUPD)) },
2102 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2103 { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
2104 { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
2105 { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
2107 PIN_CFG_PUPD)) },
2109 PIN_CFG_PUPD)) },
2111 PIN_CFG_PUPD)) },
2113 PIN_CFG_PUPD)) },
2115 PIN_CFG_PUPD)) },
2117 PIN_CFG_PUPD)) },
2119 PIN_CFG_PUPD)) },
2121 PIN_CFG_PUPD)) },
2124 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2127 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2129 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2131 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2133 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2135 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2137 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2139 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2141 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2144 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2146 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2148 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2150 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2152 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2156 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2158 PIN_CFG_PUPD)) },
2159 { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
2161 PIN_CFG_PUPD)) },
2163 PIN_CFG_PUPD)) },
2164 { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
2165 { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
2167 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2168 { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
2169 { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
2171 PIN_CFG_PUPD)) },
2173 PIN_CFG_PUPD)) },
2175 PIN_CFG_PUPD)) },
2177 PIN_CFG_PUPD)) },
2178 { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
2179 { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
2180 { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
2181 { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
2183 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2185 PIN_CFG_PUPD)) },
2186 { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
2188 PIN_CFG_PUPD)) },
2190 PIN_CFG_PUPD)) },
2191 { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
2192 { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
2194 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2195 { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
2196 { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
2198 PIN_CFG_PUPD)) },
2200 PIN_CFG_PUPD)) },
2202 PIN_CFG_PUPD)) },
2204 PIN_CFG_PUPD)) },
2205 { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
2206 { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
2207 { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
2208 { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },