Lines Matching +full:pin +full:- +full:settings
1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L Pin Control and GPIO driver core
24 #include <linux/pinctrl/pinconf-generic.h>
29 #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
30 #include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
31 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
37 #define DRV_NAME "pinctrl-rzg2l"
40 * Use 16 lower bits [15:0] for pin identifier
41 * Use 16 higher bits [31:16] for pin mux function
46 /* PIN capabilities */
62 #define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */
63 #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */
67 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
94 * and f is pin configuration capabilities supported.
105 * and f is pin configuration capabilities supported.
107 #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
115 * registers, b is the register bits (b * 8) and f is the pin
129 #define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \ argument
130 (FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \
138 #define PIN(off) (0x0800 + (off)) macro
183 { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 },
188 PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true),
220 * struct rzg2l_register_offsets - specific register offsets
232 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays
249 * struct rzg2l_hwcfg - hardware configuration data structure
258 * @oen_max_pin: the maximum pin number supporting output enable
305 * struct rzg2l_pinctrl_pin_settings - pin data
315 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume)
362 struct rzg2l_pinctrl_pin_settings *settings; member
373 u8 pin) in rzg2l_pinctrl_get_variable_pin_cfg() argument
377 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { in rzg2l_pinctrl_get_variable_pin_cfg()
378 u64 cfg = pctrl->data->variable_pin_cfg[i]; in rzg2l_pinctrl_get_variable_pin_cfg()
381 FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin) in rzg2l_pinctrl_get_variable_pin_cfg()
482 writeb(val, pctrl->base + offset); in rzg2l_pmc_writeb()
487 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzv2h_pmc_writeb()
490 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
491 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
492 writeb(val, pctrl->base + offset); in rzv2h_pmc_writeb()
493 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
503 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) in rzg2l_validate_pin()
504 return -EINVAL; in rzg2l_validate_pin()
506 data = pctrl->data->port_pin_configs[port]; in rzg2l_validate_pin()
508 return -EINVAL; in rzg2l_validate_pin()
514 u8 pin, u8 off, u8 func) in rzg2l_pinctrl_set_pfc_mode() argument
519 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
521 /* Set pin to 'Non-use (Hi-Z input protection)' */ in rzg2l_pinctrl_set_pfc_mode()
522 reg = readw(pctrl->base + PM(off)); in rzg2l_pinctrl_set_pfc_mode()
523 reg &= ~(PM_MASK << (pin * 2)); in rzg2l_pinctrl_set_pfc_mode()
524 writew(reg, pctrl->base + PM(off)); in rzg2l_pinctrl_set_pfc_mode()
526 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); in rzg2l_pinctrl_set_pfc_mode()
529 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
530 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
532 /* Select Pin function mode with PFC register */ in rzg2l_pinctrl_set_pfc_mode()
533 reg = readl(pctrl->base + PFC(off)); in rzg2l_pinctrl_set_pfc_mode()
534 reg &= ~(PFC_MASK << (pin * 4)); in rzg2l_pinctrl_set_pfc_mode()
535 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); in rzg2l_pinctrl_set_pfc_mode()
537 /* Switch to Peripheral pin function with PMC register */ in rzg2l_pinctrl_set_pfc_mode()
538 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
539 writeb(reg | BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
541 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); in rzg2l_pinctrl_set_pfc_mode()
543 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
551 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_set_mux()
560 return -EINVAL; in rzg2l_pinctrl_set_mux()
563 return -EINVAL; in rzg2l_pinctrl_set_mux()
565 psel_val = func->data; in rzg2l_pinctrl_set_mux()
566 pins = group->grp.pins; in rzg2l_pinctrl_set_mux()
568 for (i = 0; i < group->grp.npins; i++) { in rzg2l_pinctrl_set_mux()
569 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; in rzg2l_pinctrl_set_mux()
571 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); in rzg2l_pinctrl_set_mux() local
573 ret = rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(pins[i]), pin); in rzg2l_pinctrl_set_mux()
577 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", in rzg2l_pinctrl_set_mux()
578 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); in rzg2l_pinctrl_set_mux()
580 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); in rzg2l_pinctrl_set_mux()
596 return -ENOMEM; in rzg2l_map_add_config()
598 map->type = type; in rzg2l_map_add_config()
599 map->data.configs.group_or_pin = group_or_pin; in rzg2l_map_add_config()
600 map->data.configs.configs = cfgs; in rzg2l_map_add_config()
601 map->data.configs.num_configs = num_configs; in rzg2l_map_add_config()
627 const char *pin; in rzg2l_dt_subnode_to_map() local
631 num_pinmux = pinmux->length / sizeof(u32); in rzg2l_dt_subnode_to_map()
634 if (ret == -EINVAL) { in rzg2l_dt_subnode_to_map()
637 dev_err(pctrl->dev, "Invalid pins list in DT\n"); in rzg2l_dt_subnode_to_map()
647 dev_err(pctrl->dev, in rzg2l_dt_subnode_to_map()
649 return -EINVAL; in rzg2l_dt_subnode_to_map()
657 dev_err(pctrl->dev, "DT node must contain a config\n"); in rzg2l_dt_subnode_to_map()
658 ret = -ENODEV; in rzg2l_dt_subnode_to_map()
673 ret = -ENOMEM; in rzg2l_dt_subnode_to_map()
680 of_property_for_each_string(np, "pins", prop, pin) { in rzg2l_dt_subnode_to_map()
681 ret = rzg2l_map_add_config(&maps[idx], pin, in rzg2l_dt_subnode_to_map()
693 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
694 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), in rzg2l_dt_subnode_to_map()
696 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
698 ret = -ENOMEM; in rzg2l_dt_subnode_to_map()
702 /* Collect pin locations and mux settings from DT properties */ in rzg2l_dt_subnode_to_map()
714 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", in rzg2l_dt_subnode_to_map()
717 ret = -ENOMEM; in rzg2l_dt_subnode_to_map()
721 name = np->name; in rzg2l_dt_subnode_to_map()
734 mutex_lock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
736 /* Register a single pin group listing all the pins we read from DT */ in rzg2l_dt_subnode_to_map()
754 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
761 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); in rzg2l_dt_subnode_to_map()
768 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
822 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); in rzg2l_dt_node_to_map()
823 ret = -EINVAL; in rzg2l_dt_node_to_map()
834 void __iomem *addr = pctrl->base + offset; in rzg2l_read_pin_config()
836 /* handle _L/_H for 32-bit register read/write */ in rzg2l_read_pin_config()
838 bit -= 4; in rzg2l_read_pin_config()
848 void __iomem *addr = pctrl->base + offset; in rzg2l_rmw_pin_config()
852 /* handle _L/_H for 32-bit register read/write */ in rzg2l_rmw_pin_config()
854 bit -= 4; in rzg2l_rmw_pin_config()
858 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
861 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
867 return SD_CH(regs->sd_ch, 0); in rzg2l_caps_to_pwr_reg()
869 return SD_CH(regs->sd_ch, 1); in rzg2l_caps_to_pwr_reg()
871 return ETH_POC(regs->eth_poc, 0); in rzg2l_caps_to_pwr_reg()
873 return ETH_POC(regs->eth_poc, 1); in rzg2l_caps_to_pwr_reg()
877 return -EINVAL; in rzg2l_caps_to_pwr_reg()
880 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) in rzg2l_get_power_source() argument
882 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_get_power_source()
883 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzg2l_get_power_source()
888 return pctrl->settings[pin].power_source; in rzg2l_get_power_source()
894 val = readb(pctrl->base + pwr_reg); in rzg2l_get_power_source()
904 return -EINVAL; in rzg2l_get_power_source()
908 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) in rzg2l_set_power_source() argument
910 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_set_power_source()
911 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzg2l_set_power_source()
916 pctrl->settings[pin].power_source = ps; in rzg2l_set_power_source()
926 return -EINVAL; in rzg2l_set_power_source()
933 return -EINVAL; in rzg2l_set_power_source()
940 writeb(val, pctrl->base + pwr_reg); in rzg2l_set_power_source()
941 pctrl->settings[pin].power_source = ps; in rzg2l_set_power_source()
977 return hwcfg->iolh_groupa_ua[val]; in rzg2l_iolh_val_to_ua()
980 return hwcfg->iolh_groupb_ua[val]; in rzg2l_iolh_val_to_ua()
983 return hwcfg->iolh_groupc_ua[val]; in rzg2l_iolh_val_to_ua()
996 array = &hwcfg->iolh_groupa_ua[ps_index]; in rzg2l_iolh_ua_to_val()
999 array = &hwcfg->iolh_groupb_ua[ps_index]; in rzg2l_iolh_ua_to_val()
1002 array = &hwcfg->iolh_groupc_ua[ps_index]; in rzg2l_iolh_ua_to_val()
1005 return -EINVAL; in rzg2l_iolh_ua_to_val()
1012 return -EINVAL; in rzg2l_iolh_ua_to_val()
1019 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_ds_is_supported()
1024 array = hwcfg->iolh_groupa_ua; in rzg2l_ds_is_supported()
1027 array = hwcfg->iolh_groupb_ua; in rzg2l_ds_is_supported()
1030 array = hwcfg->iolh_groupc_ua; in rzg2l_ds_is_supported()
1049 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; in rzg2l_pin_to_oen_bit()
1051 u8 pin = RZG2L_PIN_ID_TO_PIN(_pin); in rzg2l_pin_to_oen_bit() local
1053 if (pin > pctrl->data->hwcfg->oen_max_pin) in rzg2l_pin_to_oen_bit()
1054 return -EINVAL; in rzg2l_pin_to_oen_bit()
1065 return -EINVAL; in rzg2l_pin_to_oen_bit()
1076 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); in rzg2l_read_oen()
1089 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_write_oen()
1090 val = readb(pctrl->base + ETH_MODE); in rzg2l_write_oen()
1095 writeb(val, pctrl->base + ETH_MODE); in rzg2l_write_oen()
1096 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_write_oen()
1103 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; in rzg3s_pin_to_oen_bit()
1104 u8 port, pin, bit; in rzg3s_pin_to_oen_bit() local
1107 return -EINVAL; in rzg3s_pin_to_oen_bit()
1110 pin = RZG2L_PIN_ID_TO_PIN(_pin); in rzg3s_pin_to_oen_bit()
1111 if (pin > pctrl->data->hwcfg->oen_max_pin) in rzg3s_pin_to_oen_bit()
1112 return -EINVAL; in rzg3s_pin_to_oen_bit()
1114 bit = pin * 2; in rzg3s_pin_to_oen_bit()
1115 if (port == pctrl->data->hwcfg->oen_max_port) in rzg3s_pin_to_oen_bit()
1129 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); in rzg3s_oen_read()
1142 spin_lock_irqsave(&pctrl->lock, flags); in rzg3s_oen_write()
1143 val = readb(pctrl->base + ETH_MODE); in rzg3s_oen_write()
1148 writeb(val, pctrl->base + ETH_MODE); in rzg3s_oen_write()
1149 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg3s_oen_write()
1167 return -EINVAL; in rzg2l_hw_to_bias_param()
1183 return -EINVAL; in rzg2l_bias_param_to_hw()
1200 return -EINVAL; in rzv2h_hw_to_bias_param()
1216 return -EINVAL; in rzv2h_bias_param_to_hw()
1224 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; in rzv2h_pin_to_oen_bit()
1228 if (!strcmp(pin_desc->name, pin_names[i])) in rzv2h_pin_to_oen_bit()
1242 return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); in rzv2h_oen_read()
1247 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzv2h_oen_write()
1248 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzv2h_oen_write()
1254 spin_lock_irqsave(&pctrl->lock, flags); in rzv2h_oen_write()
1255 val = readb(pctrl->base + PFC_OEN); in rzv2h_oen_write()
1261 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_oen_write()
1262 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); in rzv2h_oen_write()
1263 writeb(val, pctrl->base + PFC_OEN); in rzv2h_oen_write()
1264 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); in rzv2h_oen_write()
1265 spin_unlock_irqrestore(&pctrl->lock, flags); in rzv2h_oen_write()
1275 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_pinconf_get()
1276 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_get() local
1278 u64 *pin_data = pin->drv_data; in rzg2l_pinctrl_pinconf_get()
1286 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1296 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1302 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1305 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1310 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1311 if (!pctrl->data->oen_read) in rzg2l_pinctrl_pinconf_get()
1312 return -EOPNOTSUPP; in rzg2l_pinctrl_pinconf_get()
1313 arg = pctrl->data->oen_read(pctrl, _pin); in rzg2l_pinctrl_pinconf_get()
1315 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1327 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1336 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1339 ret = pctrl->data->hw_to_bias_param(arg); in rzg2l_pinctrl_pinconf_get()
1344 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1352 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) in rzg2l_pinctrl_pinconf_get()
1353 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1360 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; in rzg2l_pinctrl_pinconf_get()
1369 !hwcfg->drive_strength_ua) in rzg2l_pinctrl_pinconf_get()
1370 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1384 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) in rzg2l_pinctrl_pinconf_get()
1385 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1388 arg = hwcfg->iolh_groupb_oi[index]; in rzg2l_pinctrl_pinconf_get()
1395 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1399 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1401 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1406 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1410 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1415 return -EINVAL; in rzg2l_pinctrl_pinconf_get()
1421 return -ENOTSUPP; in rzg2l_pinctrl_pinconf_get()
1435 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_set() local
1436 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_pinconf_set()
1437 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; in rzg2l_pinctrl_pinconf_set() local
1438 u64 *pin_data = pin->drv_data; in rzg2l_pinctrl_pinconf_set()
1446 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1456 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1466 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1473 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1474 if (!pctrl->data->oen_write) in rzg2l_pinctrl_pinconf_set()
1475 return -EOPNOTSUPP; in rzg2l_pinctrl_pinconf_set()
1476 ret = pctrl->data->oen_write(pctrl, _pin, !!arg); in rzg2l_pinctrl_pinconf_set()
1482 settings.power_source = arg; in rzg2l_pinctrl_pinconf_set()
1487 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1496 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1498 ret = pctrl->data->bias_param_to_hw(param); in rzg2l_pinctrl_pinconf_set()
1506 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) in rzg2l_pinctrl_pinconf_set()
1507 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1511 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) in rzg2l_pinctrl_pinconf_set()
1515 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1522 !hwcfg->drive_strength_ua) in rzg2l_pinctrl_pinconf_set()
1523 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1525 settings.drive_strength_ua = arg; in rzg2l_pinctrl_pinconf_set()
1529 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) in rzg2l_pinctrl_pinconf_set()
1530 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1532 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { in rzg2l_pinctrl_pinconf_set()
1533 if (arg == hwcfg->iolh_groupb_oi[index]) in rzg2l_pinctrl_pinconf_set()
1536 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) in rzg2l_pinctrl_pinconf_set()
1537 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1545 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1553 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1560 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1563 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1568 return -EOPNOTSUPP; in rzg2l_pinctrl_pinconf_set()
1573 if (settings.power_source != pctrl->settings[_pin].power_source) { in rzg2l_pinctrl_pinconf_set()
1574 ret = rzg2l_ps_is_supported(settings.power_source); in rzg2l_pinctrl_pinconf_set()
1576 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1579 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); in rzg2l_pinctrl_pinconf_set()
1585 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { in rzg2l_pinctrl_pinconf_set()
1589 iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source); in rzg2l_pinctrl_pinconf_set()
1591 settings.drive_strength_ua); in rzg2l_pinctrl_pinconf_set()
1593 return -EINVAL; in rzg2l_pinctrl_pinconf_set()
1596 val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua); in rzg2l_pinctrl_pinconf_set()
1602 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; in rzg2l_pinctrl_pinconf_set()
1648 /* Check config matching between to pin */ in rzg2l_pinctrl_pinconf_group_get()
1650 return -EOPNOTSUPP; in rzg2l_pinctrl_pinconf_group_get()
1686 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_request()
1687 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_request()
1703 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_request()
1706 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_request()
1708 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); in rzg2l_gpio_request()
1710 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_request()
1718 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_set_direction()
1719 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_set_direction()
1725 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
1727 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_set_direction()
1731 writew(reg16, pctrl->base + PM(off)); in rzg2l_gpio_set_direction()
1733 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
1739 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_get_direction()
1740 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_get_direction()
1744 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { in rzg2l_gpio_get_direction()
1747 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_get_direction()
1770 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_set()
1771 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_set()
1777 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set()
1779 reg8 = readb(pctrl->base + P(off)); in rzg2l_gpio_set()
1782 writeb(reg8 | BIT(bit), pctrl->base + P(off)); in rzg2l_gpio_set()
1784 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); in rzg2l_gpio_set()
1786 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set()
1805 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_get()
1806 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_get()
1811 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_get()
1815 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); in rzg2l_gpio_get()
1817 return !!(readb(pctrl->base + P(off)) & BIT(bit)); in rzg2l_gpio_get()
1819 return -EINVAL; in rzg2l_gpio_get()
1828 virq = irq_find_mapping(chip->irq.domain, offset); in rzg2l_gpio_free()
1834 * drive the GPIO pin as an output. in rzg2l_gpio_free()
1964 /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */
2421 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; in rzg2l_gpio_get_gpioint()
2422 const struct rzg2l_pinctrl_data *data = pctrl->data; in rzg2l_gpio_get_gpioint()
2423 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_get_gpioint()
2429 return -EINVAL; in rzg2l_gpio_get_gpioint()
2434 if (port >= data->n_ports || in rzg2l_gpio_get_gpioint()
2435 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port]))) in rzg2l_gpio_get_gpioint()
2436 return -EINVAL; in rzg2l_gpio_get_gpioint()
2440 gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i])); in rzg2l_gpio_get_gpioint()
2448 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; in rzg2l_gpio_irq_endisable()
2449 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_irq_endisable()
2455 addr = pctrl->base + ISEL(off); in rzg2l_gpio_irq_endisable()
2457 bit -= 4; in rzg2l_gpio_irq_endisable()
2461 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_endisable()
2466 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_endisable()
2501 seq_puts(p, dev_name(gc->parent)); in rzg2l_gpio_irq_print_chip()
2511 if (!data->parent_data) in rzg2l_gpio_irq_set_wake()
2512 return -EOPNOTSUPP; in rzg2l_gpio_irq_set_wake()
2519 atomic_inc(&pctrl->wakeup_path); in rzg2l_gpio_irq_set_wake()
2521 atomic_dec(&pctrl->wakeup_path); in rzg2l_gpio_irq_set_wake()
2527 .name = "rzg2l-gpio",
2544 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_interrupt_input_mode()
2545 u64 *pin_data = pin_desc->drv_data; in rzg2l_gpio_interrupt_input_mode()
2551 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_interrupt_input_mode()
2580 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
2581 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); in rzg2l_gpio_child_to_parent_hwirq()
2582 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
2584 ret = -ENOSPC; in rzg2l_gpio_child_to_parent_hwirq()
2589 pctrl->hwirq[irq] = child; in rzg2l_gpio_child_to_parent_hwirq()
2590 irq += pctrl->data->hwcfg->tint_start_index; in rzg2l_gpio_child_to_parent_hwirq()
2604 struct irq_domain *domain = pctrl->gpio_chip.irq.domain; in rzg2l_gpio_irq_restore()
2612 if (!pctrl->hwirq[i]) in rzg2l_gpio_irq_restore()
2615 virq = irq_find_mapping(domain, pctrl->hwirq[i]); in rzg2l_gpio_irq_restore()
2617 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", in rzg2l_gpio_irq_restore()
2618 pctrl->hwirq[i]); in rzg2l_gpio_irq_restore()
2624 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); in rzg2l_gpio_irq_restore()
2632 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_restore()
2636 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_restore()
2639 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); in rzg2l_gpio_irq_restore()
2657 if (pctrl->hwirq[i] == hwirq) { in rzg2l_gpio_irq_domain_free()
2660 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
2661 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); in rzg2l_gpio_irq_domain_free()
2662 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
2663 pctrl->hwirq[i] = 0; in rzg2l_gpio_irq_domain_free()
2676 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_init_irq_valid_mask()
2680 for (offset = 0; offset < chip->ngpio; offset++) { in rzg2l_init_irq_valid_mask()
2686 if (port >= pctrl->data->n_ports || in rzg2l_init_irq_valid_mask()
2688 pctrl->data->port_pin_configs[port]))) in rzg2l_init_irq_valid_mask()
2695 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_reg_cache_alloc()
2698 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2700 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2702 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2704 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2706 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2707 if (!cache->p) in rzg2l_pinctrl_reg_cache_alloc()
2708 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2710 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2711 if (!cache->pm) in rzg2l_pinctrl_reg_cache_alloc()
2712 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2714 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2715 if (!cache->pmc) in rzg2l_pinctrl_reg_cache_alloc()
2716 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2718 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2719 if (!cache->pfc) in rzg2l_pinctrl_reg_cache_alloc()
2720 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2723 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_reg_cache_alloc()
2725 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), in rzg2l_pinctrl_reg_cache_alloc()
2727 if (!cache->iolh[i]) in rzg2l_pinctrl_reg_cache_alloc()
2728 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2730 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), in rzg2l_pinctrl_reg_cache_alloc()
2732 if (!cache->ien[i]) in rzg2l_pinctrl_reg_cache_alloc()
2733 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2735 cache->pupd[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pupd[i]), in rzg2l_pinctrl_reg_cache_alloc()
2737 if (!cache->pupd[i]) in rzg2l_pinctrl_reg_cache_alloc()
2738 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2741 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, in rzg2l_pinctrl_reg_cache_alloc()
2742 sizeof(*dedicated_cache->iolh[i]), in rzg2l_pinctrl_reg_cache_alloc()
2744 if (!dedicated_cache->iolh[i]) in rzg2l_pinctrl_reg_cache_alloc()
2745 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2747 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, in rzg2l_pinctrl_reg_cache_alloc()
2748 sizeof(*dedicated_cache->ien[i]), in rzg2l_pinctrl_reg_cache_alloc()
2750 if (!dedicated_cache->ien[i]) in rzg2l_pinctrl_reg_cache_alloc()
2751 return -ENOMEM; in rzg2l_pinctrl_reg_cache_alloc()
2754 pctrl->cache = cache; in rzg2l_pinctrl_reg_cache_alloc()
2755 pctrl->dedicated_cache = dedicated_cache; in rzg2l_pinctrl_reg_cache_alloc()
2762 struct device_node *np = pctrl->dev->of_node; in rzg2l_gpio_register()
2763 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_gpio_register()
2764 const char *name = dev_name(pctrl->dev); in rzg2l_gpio_register()
2773 return -ENXIO; in rzg2l_gpio_register()
2778 return -EPROBE_DEFER; in rzg2l_gpio_register()
2780 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); in rzg2l_gpio_register()
2782 return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n"); in rzg2l_gpio_register()
2787 of_args.args[2] != pctrl->data->n_port_pins) in rzg2l_gpio_register()
2788 return dev_err_probe(pctrl->dev, -EINVAL, in rzg2l_gpio_register()
2789 "gpio-ranges does not match selected SOC\n"); in rzg2l_gpio_register()
2791 chip->names = pctrl->data->port_pins; in rzg2l_gpio_register()
2792 chip->request = rzg2l_gpio_request; in rzg2l_gpio_register()
2793 chip->free = rzg2l_gpio_free; in rzg2l_gpio_register()
2794 chip->get_direction = rzg2l_gpio_get_direction; in rzg2l_gpio_register()
2795 chip->direction_input = rzg2l_gpio_direction_input; in rzg2l_gpio_register()
2796 chip->direction_output = rzg2l_gpio_direction_output; in rzg2l_gpio_register()
2797 chip->get = rzg2l_gpio_get; in rzg2l_gpio_register()
2798 chip->set = rzg2l_gpio_set; in rzg2l_gpio_register()
2799 chip->label = name; in rzg2l_gpio_register()
2800 chip->parent = pctrl->dev; in rzg2l_gpio_register()
2801 chip->owner = THIS_MODULE; in rzg2l_gpio_register()
2802 chip->base = -1; in rzg2l_gpio_register()
2803 chip->ngpio = of_args.args[2]; in rzg2l_gpio_register()
2805 girq = &chip->irq; in rzg2l_gpio_register()
2807 girq->fwnode = dev_fwnode(pctrl->dev); in rzg2l_gpio_register()
2808 girq->parent_domain = parent_domain; in rzg2l_gpio_register()
2809 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; in rzg2l_gpio_register()
2810 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; in rzg2l_gpio_register()
2811 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; in rzg2l_gpio_register()
2812 girq->init_valid_mask = rzg2l_init_irq_valid_mask; in rzg2l_gpio_register()
2814 pctrl->gpio_range.id = 0; in rzg2l_gpio_register()
2815 pctrl->gpio_range.pin_base = 0; in rzg2l_gpio_register()
2816 pctrl->gpio_range.base = 0; in rzg2l_gpio_register()
2817 pctrl->gpio_range.npins = chip->ngpio; in rzg2l_gpio_register()
2818 pctrl->gpio_range.name = chip->label; in rzg2l_gpio_register()
2819 pctrl->gpio_range.gc = chip; in rzg2l_gpio_register()
2820 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); in rzg2l_gpio_register()
2822 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n"); in rzg2l_gpio_register()
2824 dev_dbg(pctrl->dev, "Registered gpio controller\n"); in rzg2l_gpio_register()
2831 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_register()
2837 pctrl->desc.name = DRV_NAME; in rzg2l_pinctrl_register()
2838 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_register()
2839 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; in rzg2l_pinctrl_register()
2840 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; in rzg2l_pinctrl_register()
2841 pctrl->desc.confops = &rzg2l_pinctrl_confops; in rzg2l_pinctrl_register()
2842 pctrl->desc.owner = THIS_MODULE; in rzg2l_pinctrl_register()
2843 if (pctrl->data->num_custom_params) { in rzg2l_pinctrl_register()
2844 pctrl->desc.num_custom_params = pctrl->data->num_custom_params; in rzg2l_pinctrl_register()
2845 pctrl->desc.custom_params = pctrl->data->custom_params; in rzg2l_pinctrl_register()
2847 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items; in rzg2l_pinctrl_register()
2851 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); in rzg2l_pinctrl_register()
2853 return -ENOMEM; in rzg2l_pinctrl_register()
2855 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, in rzg2l_pinctrl_register()
2858 return -ENOMEM; in rzg2l_pinctrl_register()
2860 pctrl->pins = pins; in rzg2l_pinctrl_register()
2861 pctrl->desc.pins = pins; in rzg2l_pinctrl_register()
2863 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { in rzg2l_pinctrl_register()
2865 pins[i].name = pctrl->data->port_pins[i]; in rzg2l_pinctrl_register()
2868 pin_data[i] = pctrl->data->port_pin_configs[j]; in rzg2l_pinctrl_register()
2877 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_register()
2878 unsigned int index = pctrl->data->n_port_pins + i; in rzg2l_pinctrl_register()
2881 pins[index].name = pctrl->data->dedicated_pins[i].name; in rzg2l_pinctrl_register()
2882 pin_data[index] = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_register()
2886 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), in rzg2l_pinctrl_register()
2888 if (!pctrl->settings) in rzg2l_pinctrl_register()
2889 return -ENOMEM; in rzg2l_pinctrl_register()
2891 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { in rzg2l_pinctrl_register()
2893 pctrl->settings[i].power_source = 3300; in rzg2l_pinctrl_register()
2898 pctrl->settings[i].power_source = ret; in rzg2l_pinctrl_register()
2906 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, in rzg2l_pinctrl_register()
2907 &pctrl->pctl); in rzg2l_pinctrl_register()
2909 return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n"); in rzg2l_pinctrl_register()
2911 ret = pinctrl_enable(pctrl->pctl); in rzg2l_pinctrl_register()
2913 return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n"); in rzg2l_pinctrl_register()
2917 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n"); in rzg2l_pinctrl_register()
2942 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in rzg2l_pinctrl_probe()
2944 return -ENOMEM; in rzg2l_pinctrl_probe()
2946 pctrl->dev = &pdev->dev; in rzg2l_pinctrl_probe()
2948 pctrl->data = of_device_get_match_data(&pdev->dev); in rzg2l_pinctrl_probe()
2949 if (!pctrl->data) in rzg2l_pinctrl_probe()
2950 return -EINVAL; in rzg2l_pinctrl_probe()
2952 pctrl->base = devm_platform_ioremap_resource(pdev, 0); in rzg2l_pinctrl_probe()
2953 if (IS_ERR(pctrl->base)) in rzg2l_pinctrl_probe()
2954 return PTR_ERR(pctrl->base); in rzg2l_pinctrl_probe()
2956 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); in rzg2l_pinctrl_probe()
2957 if (IS_ERR(pctrl->clk)) { in rzg2l_pinctrl_probe()
2958 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), in rzg2l_pinctrl_probe()
2962 spin_lock_init(&pctrl->lock); in rzg2l_pinctrl_probe()
2963 spin_lock_init(&pctrl->bitmap_lock); in rzg2l_pinctrl_probe()
2964 mutex_init(&pctrl->mutex); in rzg2l_pinctrl_probe()
2965 atomic_set(&pctrl->wakeup_path, 0); in rzg2l_pinctrl_probe()
2973 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); in rzg2l_pinctrl_probe()
2979 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_pm_setup_regs()
2980 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_pm_setup_regs()
2988 cfg = pctrl->data->port_pin_configs[port]; in rzg2l_pinctrl_pm_setup_regs()
2998 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); in rzg2l_pinctrl_pm_setup_regs()
3004 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); in rzg2l_pinctrl_pm_setup_regs()
3006 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), in rzg2l_pinctrl_pm_setup_regs()
3007 cache->iolh[0][port]); in rzg2l_pinctrl_pm_setup_regs()
3009 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, in rzg2l_pinctrl_pm_setup_regs()
3010 cache->iolh[1][port]); in rzg2l_pinctrl_pm_setup_regs()
3015 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), in rzg2l_pinctrl_pm_setup_regs()
3016 cache->pupd[0][port]); in rzg2l_pinctrl_pm_setup_regs()
3018 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), in rzg2l_pinctrl_pm_setup_regs()
3019 cache->pupd[1][port]); in rzg2l_pinctrl_pm_setup_regs()
3023 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); in rzg2l_pinctrl_pm_setup_regs()
3024 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); in rzg2l_pinctrl_pm_setup_regs()
3027 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), in rzg2l_pinctrl_pm_setup_regs()
3028 cache->ien[0][port]); in rzg2l_pinctrl_pm_setup_regs()
3030 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, in rzg2l_pinctrl_pm_setup_regs()
3031 cache->ien[1][port]); in rzg2l_pinctrl_pm_setup_regs()
3039 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; in rzg2l_pinctrl_pm_setup_dedicated_regs()
3044 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same in rzg2l_pinctrl_pm_setup_dedicated_regs()
3047 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_pm_setup_dedicated_regs()
3053 cfg = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_pm_setup_dedicated_regs()
3055 if (i + 1 < pctrl->data->n_dedicated_pins) { in rzg2l_pinctrl_pm_setup_dedicated_regs()
3056 next_cfg = pctrl->data->dedicated_pins[i + 1].config; in rzg2l_pinctrl_pm_setup_dedicated_regs()
3072 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), in rzg2l_pinctrl_pm_setup_dedicated_regs()
3073 cache->iolh[0][i]); in rzg2l_pinctrl_pm_setup_dedicated_regs()
3076 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), in rzg2l_pinctrl_pm_setup_dedicated_regs()
3077 cache->ien[0][i]); in rzg2l_pinctrl_pm_setup_dedicated_regs()
3083 pctrl->base + IOLH(off) + 4, in rzg2l_pinctrl_pm_setup_dedicated_regs()
3084 cache->iolh[1][i]); in rzg2l_pinctrl_pm_setup_dedicated_regs()
3088 pctrl->base + IEN(off) + 4, in rzg2l_pinctrl_pm_setup_dedicated_regs()
3089 cache->ien[1][i]); in rzg2l_pinctrl_pm_setup_dedicated_regs()
3098 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_pm_setup_pfc()
3101 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_pm_setup_pfc()
3102 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); in rzg2l_pinctrl_pm_setup_pfc()
3111 u8 pin; in rzg2l_pinctrl_pm_setup_pfc() local
3113 cfg = pctrl->data->port_pin_configs[port]; in rzg2l_pinctrl_pm_setup_pfc()
3118 pm = readw(pctrl->base + PM(off)); in rzg2l_pinctrl_pm_setup_pfc()
3119 for_each_set_bit(pin, &pinmap, max_pin) { in rzg2l_pinctrl_pm_setup_pfc()
3120 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_pm_setup_pfc()
3123 if (!(cache->pmc[port] & BIT(pin))) in rzg2l_pinctrl_pm_setup_pfc()
3126 /* Set pin to 'Non-use (Hi-Z input protection)' */ in rzg2l_pinctrl_pm_setup_pfc()
3127 pm &= ~(PM_MASK << (pin * 2)); in rzg2l_pinctrl_pm_setup_pfc()
3128 writew(pm, pctrl->base + PM(off)); in rzg2l_pinctrl_pm_setup_pfc()
3131 pmc &= ~BIT(pin); in rzg2l_pinctrl_pm_setup_pfc()
3132 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
3134 /* Select Pin function mode. */ in rzg2l_pinctrl_pm_setup_pfc()
3135 pfc &= ~(PFC_MASK << (pin * 4)); in rzg2l_pinctrl_pm_setup_pfc()
3136 pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4))); in rzg2l_pinctrl_pm_setup_pfc()
3137 writel(pfc, pctrl->base + PFC(off)); in rzg2l_pinctrl_pm_setup_pfc()
3139 /* Switch to Peripheral pin function. */ in rzg2l_pinctrl_pm_setup_pfc()
3140 pmc |= BIT(pin); in rzg2l_pinctrl_pm_setup_pfc()
3141 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
3145 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); in rzg2l_pinctrl_pm_setup_pfc()
3146 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_pm_setup_pfc()
3152 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_suspend_noirq()
3153 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzg2l_pinctrl_suspend_noirq()
3154 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_suspend_noirq()
3160 if (regs->sd_ch) in rzg2l_pinctrl_suspend_noirq()
3161 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); in rzg2l_pinctrl_suspend_noirq()
3162 if (regs->eth_poc) in rzg2l_pinctrl_suspend_noirq()
3163 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); in rzg2l_pinctrl_suspend_noirq()
3166 cache->qspi = readb(pctrl->base + QSPI); in rzg2l_pinctrl_suspend_noirq()
3167 cache->eth_mode = readb(pctrl->base + ETH_MODE); in rzg2l_pinctrl_suspend_noirq()
3169 if (!atomic_read(&pctrl->wakeup_path)) in rzg2l_pinctrl_suspend_noirq()
3170 clk_disable_unprepare(pctrl->clk); in rzg2l_pinctrl_suspend_noirq()
3180 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_resume_noirq()
3181 const struct rzg2l_register_offsets *regs = &hwcfg->regs; in rzg2l_pinctrl_resume_noirq()
3182 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_resume_noirq()
3185 if (!atomic_read(&pctrl->wakeup_path)) { in rzg2l_pinctrl_resume_noirq()
3186 ret = clk_prepare_enable(pctrl->clk); in rzg2l_pinctrl_resume_noirq()
3191 writeb(cache->qspi, pctrl->base + QSPI); in rzg2l_pinctrl_resume_noirq()
3192 writeb(cache->eth_mode, pctrl->base + ETH_MODE); in rzg2l_pinctrl_resume_noirq()
3194 if (regs->sd_ch) in rzg2l_pinctrl_resume_noirq()
3195 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); in rzg2l_pinctrl_resume_noirq()
3196 if (regs->eth_poc) in rzg2l_pinctrl_resume_noirq()
3197 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); in rzg2l_pinctrl_resume_noirq()
3210 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzg2l_pwpr_pfc_lock_unlock()
3213 /* Set the PWPR register to be write-protected */ in rzg2l_pwpr_pfc_lock_unlock()
3214 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3215 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3218 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3219 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ in rzg2l_pwpr_pfc_lock_unlock()
3225 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzv2h_pwpr_pfc_lock_unlock()
3229 /* Set the PWPR register to be write-protected */ in rzv2h_pwpr_pfc_lock_unlock()
3230 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3231 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3234 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3235 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3283 .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */
3419 .compatible = "renesas,r9a07g043-pinctrl",
3423 .compatible = "renesas,r9a07g044-pinctrl",
3427 .compatible = "renesas,r9a08g045-pinctrl",
3431 .compatible = "renesas,r9a09g047-pinctrl",
3435 .compatible = "renesas,r9a09g056-pinctrl",
3439 .compatible = "renesas,r9a09g057-pinctrl",
3465 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
3466 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");