Lines Matching +full:mux +full:- +full:int +full:- +full:port
1 // SPDX-License-Identifier: GPL-2.0
26 #define DRIVER_NAME "pinctrl-rza2"
34 * Use 16 higher bits [31:16] for pin mux function
51 int npins;
55 #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
56 #define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
57 #define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
58 #define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
59 #define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
60 #define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
62 #define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
63 #define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */
64 #define RZA2_PPOC 0x0900 /* Dedicated Pins 32-bit */
65 #define RZA2_PHMOMO 0x0980 /* Peripheral Pins 32-bit */
66 #define RZA2_PCKIO 0x09d0 /* CKIO Drive 8-bit */
76 static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin,
83 /* Set pin to 'Non-use (Hi-z input protection)' */
84 reg16 = readw(pfc_base + RZA2_PDR(port));
87 writew(reg16, pfc_base + RZA2_PDR(port));
90 reg8 = readb(pfc_base + RZA2_PMR(port));
92 writeb(reg8, pfc_base + RZA2_PMR(port));
99 writeb(func, pfc_base + RZA2_PFS(port, pin));
105 /* Port Mode : Peripheral module pin functions */
106 reg8 = readb(pfc_base + RZA2_PMR(port));
108 writeb(reg8, pfc_base + RZA2_PMR(port));
111 static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
114 u8 port = RZA2_PIN_ID_TO_PORT(offset);
119 reg16 = readw(pfc_base + RZA2_PDR(port));
128 writew(reg16, pfc_base + RZA2_PDR(port));
131 static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
134 u8 port = RZA2_PIN_ID_TO_PORT(offset);
138 reg16 = readw(priv->base + RZA2_PDR(port));
148 * This GPIO controller has a default Hi-Z state that is not input or
151 rza2_pin_to_gpio(priv->base, offset, 1);
156 static int rza2_chip_direction_input(struct gpio_chip *chip,
157 unsigned int offset)
161 rza2_pin_to_gpio(priv->base, offset, 1);
166 static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
169 u8 port = RZA2_PIN_ID_TO_PORT(offset);
172 return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
175 static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
176 int value)
179 u8 port = RZA2_PIN_ID_TO_PORT(offset);
183 new_value = readb(priv->base + RZA2_PODR(port));
190 writeb(new_value, priv->base + RZA2_PODR(port));
193 static int rza2_chip_direction_output(struct gpio_chip *chip,
194 unsigned int offset, int val)
199 rza2_pin_to_gpio(priv->base, offset, 0);
223 /* port I does not exist */
232 .base = -1,
242 static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
244 struct device_node *np = priv->dev->of_node;
246 int ret;
248 chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
250 return -ENOMEM;
252 chip.parent = priv->dev;
253 chip.ngpio = priv->npins;
255 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
258 dev_err(priv->dev, "Unable to parse gpio-ranges\n");
266 (of_args.args[2] != priv->npins)) {
267 dev_err(priv->dev, "gpio-ranges does not match selected SOC\n");
268 return -EINVAL;
270 priv->gpio_range.id = 0;
271 priv->gpio_range.pin_base = priv->gpio_range.base = 0;
272 priv->gpio_range.npins = priv->npins;
273 priv->gpio_range.name = chip.label;
274 priv->gpio_range.gc = &chip;
277 ret = devm_gpiochip_add_data(priv->dev, &chip, priv);
282 pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range);
284 dev_dbg(priv->dev, "Registered gpio controller\n");
289 static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv)
292 unsigned int i;
293 int ret;
295 pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL);
297 return -ENOMEM;
299 priv->pins = pins;
300 priv->desc.pins = pins;
301 priv->desc.npins = priv->npins;
303 for (i = 0; i < priv->npins; i++) {
308 ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv,
309 &priv->pctl);
311 dev_err(priv->dev, "pinctrl registration failed\n");
315 ret = pinctrl_enable(priv->pctl);
317 dev_err(priv->dev, "pinctrl enable failed\n");
323 dev_err(priv->dev, "GPIO registration failed\n");
335 static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev,
338 unsigned int *num_maps)
341 unsigned int *pins, *psel_val;
342 int i, ret, npins, gsel, fsel;
349 dev_info(priv->dev, "Missing pinmux property\n");
350 return -ENOENT;
352 npins = of_pins->length / sizeof(u32);
354 pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL);
355 psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val),
357 pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL);
359 return -ENOMEM;
361 /* Collect pin locations and mux settings from DT properties */
372 mutex_lock(&priv->mutex);
375 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
385 pin_fn[0] = np->name;
386 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
393 dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins);
395 /* Create map where to retrieve function and mux settings from */
399 ret = -ENOMEM;
403 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
404 (*map)->data.mux.group = np->name;
405 (*map)->data.mux.function = np->name;
408 mutex_unlock(&priv->mutex);
419 mutex_unlock(&priv->mutex);
421 dev_err(priv->dev, "Unable to parse DT node %s\n", np->name);
427 struct pinctrl_map *map, unsigned int num_maps)
440 static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
441 unsigned int group)
445 unsigned int i, *psel_val;
450 return -EINVAL;
454 return -EINVAL;
456 psel_val = func->data;
458 for (i = 0; i < grp->grp.npins; ++i) {
459 dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
460 port_names[RZA2_PIN_ID_TO_PORT(grp->grp.pins[i])],
461 RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]),
464 priv->base,
465 RZA2_PIN_ID_TO_PORT(grp->grp.pins[i]),
466 RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]),
481 static int rza2_pinctrl_probe(struct platform_device *pdev)
484 int ret;
486 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
488 return -ENOMEM;
490 priv->dev = &pdev->dev;
492 priv->base = devm_platform_ioremap_resource(pdev, 0);
493 if (IS_ERR(priv->base))
494 return PTR_ERR(priv->base);
496 mutex_init(&priv->mutex);
500 priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) *
503 priv->desc.name = DRIVER_NAME;
504 priv->desc.pctlops = &rza2_pinctrl_ops;
505 priv->desc.pmxops = &rza2_pinmux_ops;
506 priv->desc.owner = THIS_MODULE;
512 dev_info(&pdev->dev, "Registered ports P0 - P%c\n",
513 port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]);
519 { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
531 static int __init rza2_pinctrl_init(void)