Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:f_
1 // SPDX-License-Identifier: GPL-2.0
3 * R8A779H0 processor support - PFC hardware block.
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
61 * F_() : just information
66 #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
67 #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
68 #define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0)
69 #define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28)
70 #define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24)
71 #define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20)
72 #define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16)
73 #define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12)
74 #define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8)
75 #define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)
76 #define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)
77 #define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)
78 #define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24)
79 #define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20)
80 #define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16)
81 #define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12)
82 #define GPSR0_2 F_(GP0_02, IP0SR0_11_8)
83 #define GPSR0_1 F_(GP0_01, IP0SR0_7_4)
84 #define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
87 #define GPSR1_29 F_(ERROROUTC_N_A, IP3SR1_23_20)
88 #define GPSR1_28 F_(HTX3, IP3SR1_19_16)
89 #define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12)
90 #define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8)
91 #define GPSR1_25 F_(HSCK3, IP3SR1_7_4)
92 #define GPSR1_24 F_(HRX3, IP3SR1_3_0)
93 #define GPSR1_23 F_(GP1_23, IP2SR1_31_28)
94 #define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)
95 #define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)
96 #define GPSR1_20 F_(SSI_SD, IP2SR1_19_16)
97 #define GPSR1_19 F_(SSI_WS, IP2SR1_15_12)
98 #define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8)
99 #define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4)
100 #define GPSR1_16 F_(HRX0, IP2SR1_3_0)
101 #define GPSR1_15 F_(HSCK0, IP1SR1_31_28)
102 #define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24)
103 #define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20)
104 #define GPSR1_12 F_(HTX0, IP1SR1_19_16)
105 #define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12)
106 #define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8)
107 #define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4)
108 #define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0)
109 #define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28)
110 #define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24)
111 #define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20)
112 #define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16)
113 #define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12)
114 #define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8)
115 #define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4)
116 #define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0)
119 #define GPSR2_19 F_(CANFD1_RX, IP2SR2_15_12)
120 #define GPSR2_17 F_(CANFD1_TX, IP2SR2_7_4)
121 #define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28)
122 #define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24)
123 #define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20)
124 #define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16)
125 #define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)
126 #define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)
127 #define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)
128 #define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0)
129 #define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28)
130 #define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)
131 #define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20)
132 #define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)
133 #define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)
134 #define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)
135 #define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4)
136 #define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)
139 #define GPSR3_31 F_(TCLK4, IP3SR3_31_28)
140 #define GPSR3_30 F_(TCLK3, IP3SR3_27_24)
141 #define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20)
142 #define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16)
143 #define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12)
144 #define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8)
145 #define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4)
146 #define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0)
147 #define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28)
148 #define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24)
149 #define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20)
150 #define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16)
151 #define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12)
152 #define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8)
153 #define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4)
154 #define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0)
155 #define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28)
156 #define GPSR3_14 F_(PWM2, IP1SR3_27_24)
157 #define GPSR3_13 F_(PWM1, IP1SR3_23_20)
158 #define GPSR3_12 F_(SD_WP, IP1SR3_19_16)
159 #define GPSR3_11 F_(SD_CD, IP1SR3_15_12)
160 #define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8)
161 #define GPSR3_9 F_(MMC_D6, IP1SR3_7_4)
162 #define GPSR3_8 F_(MMC_D7, IP1SR3_3_0)
163 #define GPSR3_7 F_(MMC_D4, IP0SR3_31_28)
164 #define GPSR3_6 F_(MMC_D5, IP0SR3_27_24)
165 #define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20)
166 #define GPSR3_4 F_(MMC_DS, IP0SR3_19_16)
167 #define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12)
168 #define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8)
169 #define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4)
170 #define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0)
173 #define GPSR4_24 F_(AVS1, IP3SR4_3_0)
174 #define GPSR4_23 F_(AVS0, IP2SR4_31_28)
175 #define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20)
176 #define GPSR4_15 F_(PWM4, IP1SR4_31_28)
177 #define GPSR4_14 F_(PWM3, IP1SR4_27_24)
178 #define GPSR4_13 F_(HSCK2, IP1SR4_23_20)
179 #define GPSR4_12 F_(HCTS2_N, IP1SR4_19_16)
180 #define GPSR4_11 F_(SCIF_CLK2, IP1SR4_15_12)
181 #define GPSR4_10 F_(HRTS2_N, IP1SR4_11_8)
182 #define GPSR4_9 F_(HTX2, IP1SR4_7_4)
183 #define GPSR4_8 F_(HRX2, IP1SR4_3_0)
184 #define GPSR4_7 F_(SDA3, IP0SR4_31_28)
185 #define GPSR4_6 F_(SCL3, IP0SR4_27_24)
186 #define GPSR4_5 F_(SDA2, IP0SR4_23_20)
187 #define GPSR4_4 F_(SCL2, IP0SR4_19_16)
188 #define GPSR4_3 F_(SDA1, IP0SR4_15_12)
189 #define GPSR4_2 F_(SCL1, IP0SR4_11_8)
190 #define GPSR4_1 F_(SDA0, IP0SR4_7_4)
191 #define GPSR4_0 F_(SCL0, IP0SR4_3_0)
194 #define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16)
195 #define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12)
196 #define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8)
197 #define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4)
198 #define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0)
199 #define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28)
200 #define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24)
201 #define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20)
202 #define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16)
203 #define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12)
204 #define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8)
205 #define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4)
206 #define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0)
207 #define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28)
208 #define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24)
209 #define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20)
210 #define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16)
211 #define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12)
212 #define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8)
213 #define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4)
214 #define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0)
217 #define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
218 #define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)
219 #define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)
220 #define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)
221 #define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)
222 #define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)
223 #define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)
224 #define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)
225 #define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)
226 #define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)
227 #define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)
228 #define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)
229 #define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)
230 #define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)
231 #define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)
232 #define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)
233 #define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)
234 #define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)
235 #define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)
236 #define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)
237 #define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)
240 #define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)
241 #define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)
242 #define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)
243 #define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)
244 #define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)
245 #define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)
246 #define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)
247 #define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)
248 #define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)
249 #define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)
250 #define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)
251 #define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)
252 #define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)
253 #define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)
254 #define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)
255 #define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)
256 #define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)
257 #define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)
258 #define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)
259 #define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
260 #define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
264 /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
265 …F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
266 … F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
267 … F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
268 …(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
269 …(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
270 …(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
271 …MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
272 …F5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
274 /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
275 …F5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
276 …5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
277 …F5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
278 …F5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
279 …F5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
280 …LK1_A) FM(IRQ2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
281 …HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
282 …HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
284 /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
285 …N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
286 …N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
287 …CK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
290 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
291 …HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
292 …S3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
293 …N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
294 …3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
295 …RX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
296 …F1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
297 …HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
298 …HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
300 /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
301 …N_B) FM(CTS1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
302 …N_B) FM(RTS1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
303 …CK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
304 …F0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
305 …0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
306 … FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
307 …TS0_N) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
308 …(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
310 /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
311 …0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
312 … FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
313 … FM(TCLK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
314 … FM(TCLK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
315 … FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
316 …) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
317 … FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
318 …F_(0, 0) FM(TCLK2_A) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
320 /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
321 …A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
322 …OF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
323 …OF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
324 …A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
325 …) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
326 …UTC_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
329 /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
330 …TXDA) F_(0, 0) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
331 …A_N_A) F_(0, 0) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
332 …EXTFXR) F_(0, 0) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
333 …XTFXR) F_(0, 0) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
334 …EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
335 …ENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
336 …R_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
337 …TO1_A) F_(0, 0) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
339 /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
340 …TO0_A) F_(0, 0) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
341 …XR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
342 …XR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
343 …STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
344 …(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
345 …FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
346 …D3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
347 …D3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
349 /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
350 …D1_TX) F_(0, 0) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
351 …D1_RX) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
354 /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
355 …_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
356 …_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
357 …_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
358 …SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
359 …MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
360 …_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
361 …MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
362 …MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
364 /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
365 …MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
366 …MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
367 …SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
368 …(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
369 …(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
370 …PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
371 …PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
372 …I0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
374 /* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
375 …I0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
376 …I0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
377 …ISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
378 …OSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
379 …_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
380 …OSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
381 …_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
382 …ISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
384 /* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
385 …I1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
386 …I1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
387 …I1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
388 …ESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
389 …C_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
390 …_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
391 …CLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
392 …CLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
395 /* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
396 …M(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
397 …M(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
398 …M(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
399 …M(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
400 …M(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
401 …M(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
402 …M(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
403 …M(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
405 /* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
406 …2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
407 … FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
408 … FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
409 …F_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
410 …N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
411 …2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
412 …PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
413 …M(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
415 /* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
416 …LKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
417 …M(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
419 /* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
420 …M(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
423 /* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
424 …er_GPTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
425 …GPTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
426 …r_GPTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
427 …2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
428 …PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
429 …er_GPTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
430 …B2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
431 …CREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
433 /* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
434 …B2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
435 …B2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
436 …2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
437 …B2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
438 …B2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
439 …B2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
440 …B2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
441 …B2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
443 /* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
444 …B2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
445 …B2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
446 …B2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
447 …TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
448 …RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
451 /* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
452 …1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
453 …_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
454 …B1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
455 …PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
456 …B1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
457 …B1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
458 …AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
459 …B1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
461 /* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
462 …AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
463 …B1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
464 …AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
465 …AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
466 …AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
467 …AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
468 …AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
469 …AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
471 /* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
472 …AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
473 …AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
474 …AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
475 …AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
476 …CREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
479 /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
480 …AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
481 …AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
482 …ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
483 …AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
484 …B0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
485 …PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
486 …AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
487 …AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
489 /* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
490 …AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
491 …CREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
492 …_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
493 …AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
494 …AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
495 …B0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
496 …0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
497 …AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
499 /* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D …
500 …B0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
501 …AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
502 …AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
503 …AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
504 …B0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
614 /* MOD_SEL4 */ /* 0 */ /* 1 */
636 PINMUX_RESERVED = 0,
642 #define F_(x, y) macro
650 #undef F_
653 #define F_(x, y) macro
660 #undef F_
1182 * Pins not associated with a GPIO port.
1194 /* - AUDIO CLOCK ----------------------------------------- */
1210 /* - AVB0 ------------------------------------------------ */
1253 RCAR_GP_PIN(7, 0),
1285 RCAR_GP_PIN(7, 9),
1292 RCAR_GP_PIN(7, 0),
1312 /* - AVB1 ------------------------------------------------ */
1336 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1354 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11),
1373 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),
1414 /* - AVB2 ------------------------------------------------ */
1453 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),
1472 RCAR_GP_PIN(5, 0),
1492 /* - CANFD0 ----------------------------------------------------------------- */
1501 /* - CANFD1 ----------------------------------------------------------------- */
1510 /* - CANFD2 ----------------------------------------------------------------- */
1519 /* - CANFD3 ----------------------------------------------------------------- */
1528 /* - CANFD Clock ------------------------------------------------------------ */
1531 RCAR_GP_PIN(2, 9),
1537 /* - HSCIF0 ----------------------------------------------------------------- */
1560 /* - HSCIF1 ------------------------------------------------------------------- */
1563 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1570 RCAR_GP_PIN(0, 18),
1577 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1599 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1605 /* - HSCIF2 ----------------------------------------------------------------- */
1608 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1628 /* - HSCIF3 ------------------------------------------------------------------- */
1653 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1673 /* - I2C0 ------------------------------------------------------------------- */
1676 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1682 /* - I2C1 ------------------------------------------------------------------- */
1691 /* - I2C2 ------------------------------------------------------------------- */
1700 /* - I2C3 ------------------------------------------------------------------- */
1709 /* - INTC-EX ---------------------------------------------------------------- */
1712 RCAR_GP_PIN(0, 6),
1727 RCAR_GP_PIN(0, 5),
1742 RCAR_GP_PIN(0, 4),
1749 RCAR_GP_PIN(0, 13),
1757 RCAR_GP_PIN(0, 3),
1793 /* - MMC -------------------------------------------------------------------- */
1795 /* MMC_SD_D[0:3], MMC_D[4:7] */
1796 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1799 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1836 /* - MSIOF0 ----------------------------------------------------------------- */
1867 RCAR_GP_PIN(1, 9),
1880 /* - MSIOF1 ----------------------------------------------------------------- */
1904 RCAR_GP_PIN(1, 0),
1924 /* - MSIOF2 ----------------------------------------------------------------- */
1927 RCAR_GP_PIN(0, 17),
1934 RCAR_GP_PIN(0, 15),
1941 RCAR_GP_PIN(0, 14),
1948 RCAR_GP_PIN(0, 13),
1955 RCAR_GP_PIN(0, 16),
1962 RCAR_GP_PIN(0, 18),
1968 /* - MSIOF3 ----------------------------------------------------------------- */
1971 RCAR_GP_PIN(0, 3),
1978 RCAR_GP_PIN(0, 6),
1985 RCAR_GP_PIN(0, 1),
1992 RCAR_GP_PIN(0, 2),
1999 RCAR_GP_PIN(0, 4),
2006 RCAR_GP_PIN(0, 5),
2012 /* - MSIOF4 ----------------------------------------------------------------- */
2056 /* - MSIOF5 ----------------------------------------------------------------- */
2059 RCAR_GP_PIN(0, 11),
2066 RCAR_GP_PIN(0, 9),
2073 RCAR_GP_PIN(0, 8),
2080 RCAR_GP_PIN(0, 7),
2087 RCAR_GP_PIN(0, 10),
2094 RCAR_GP_PIN(0, 12),
2100 /* - PCIE ------------------------------------------------------------------- */
2110 /* - PWM0 --------------------------------------------------------------------- */
2127 /* - PWM1 --------------------------------------------------------------------- */
2152 /* - PWM2 --------------------------------------------------------------------- */
2177 /* - PWM3 --------------------------------------------------------------------- */
2202 /* - PWM4 ------------------------------------------------------------------- */
2211 /* - QSPI0 ------------------------------------------------------------------ */
2229 /* - QSPI1 ------------------------------------------------------------------ */
2247 /* - SCIF0 ------------------------------------------------------------------ */
2270 /* - SCIF1 -------------------------------------------------------------------- */
2273 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2280 RCAR_GP_PIN(0, 18),
2287 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2309 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2315 /* - SCIF3 -------------------------------------------------------------------- */
2340 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2360 /* - SCIF4 ------------------------------------------------------------------ */
2377 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 9),
2383 /* - SCIF Clock ------------------------------------------------------------- */
2400 /* - SSI ------------------------------------------------- */
2416 /* - TPU --------------------------------------------------------------------- */
2462 RCAR_GP_PIN(2, 0),
3001 #define F_(x, y) FN_##y macro
3003 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
3004 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3028 { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(
3029 0, 0,
3030 0, 0,
3062 { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
3063 GROUP(-12, 1, -1, 1, -1, 1, 1, 1, 1, 1, 1,
3088 { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(
3122 { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060040, 32,
3123 GROUP(-7, 1, 1, -1, 1, -5, 1, 1, 1, 1, 1,
3149 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
3150 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3176 { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
3177 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3203 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
3204 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3230 #undef F_
3233 #define F_(x, y) x, macro
3235 { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(
3245 { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(
3255 { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
3256 GROUP(-20, 4, 4, 4),
3263 { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(
3273 { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(
3283 { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(
3293 { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
3294 GROUP(-8, 4, 4, 4, 4, 4, 4),
3304 { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(
3314 { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(
3324 { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
3325 GROUP(-16, 4, -4, 4, -4),
3333 { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(
3343 { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(
3353 { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(
3363 { PINMUX_CFG_REG("IP3SR3", 0xE605886C, 32, 4, GROUP(
3373 { PINMUX_CFG_REG("IP0SR4", 0xE6060060, 32, 4, GROUP(
3383 { PINMUX_CFG_REG("IP1SR4", 0xE6060064, 32, 4, GROUP(
3393 { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32,
3394 GROUP(4, -4, 4, -20),
3401 { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32,
3402 GROUP(-28, 4),
3407 { PINMUX_CFG_REG("IP0SR5", 0xE6060860, 32, 4, GROUP(
3417 { PINMUX_CFG_REG("IP1SR5", 0xE6060864, 32, 4, GROUP(
3427 { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32,
3428 GROUP(-12, 4, 4, 4, 4, 4),
3437 { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
3447 { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(
3457 { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,
3458 GROUP(-12, 4, 4, 4, 4, 4),
3467 { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(
3477 { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(
3487 { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,
3488 GROUP(-12, 4, 4, 4, 4, 4),
3497 #undef F_
3500 #define F_(x, y) x, macro
3502 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32,
3503 GROUP(-24, 1, 1, 1, 1, 1, 1, 1, 1),
3505 /* RESERVED 31-8 */
3519 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {
3520 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */
3521 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */
3522 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */
3523 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */
3524 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */
3525 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */
3526 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */
3527 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */
3529 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {
3530 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */
3531 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */
3532 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */
3533 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */
3534 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */
3535 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */
3536 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */
3537 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */
3539 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {
3540 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */
3541 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */
3542 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */
3544 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {
3552 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */
3554 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {
3561 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */
3562 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */
3564 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {
3572 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */
3574 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {
3580 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */
3582 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {
3590 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */
3592 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {
3599 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */
3600 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */
3602 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {
3606 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {
3614 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */
3616 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {
3623 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/
3624 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */
3626 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {
3634 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */
3636 { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {
3644 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */
3646 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {
3654 { RCAR_GP_PIN(4, 0), 0, 3 }, /* SCL0 */
3656 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {
3663 { RCAR_GP_PIN(4, 9), 4, 3 }, /* HTX2 */
3664 { RCAR_GP_PIN(4, 8), 0, 3 }, /* HRX2 */
3666 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {
3670 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {
3671 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */
3673 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {
3681 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */
3683 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {
3690 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */
3691 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */
3693 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {
3698 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */
3700 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {
3708 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */
3710 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {
3717 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */
3718 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */
3720 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {
3725 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */
3727 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {
3735 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */
3737 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {
3744 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */
3745 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */
3747 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {
3752 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */
3768 [POC0] = { 0xE60500A0, },
3769 [POC1] = { 0xE60508A0, },
3770 [POC3] = { 0xE60588A0, },
3771 [POC4] = { 0xE60600A0, },
3772 [POC5] = { 0xE60608A0, },
3773 [POC6] = { 0xE60610A0, },
3774 [POC7] = { 0xE60618A0, },
3780 int bit = pin & 0x1f; in r8a779h0_pin_to_pocctrl()
3783 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18): in r8a779h0_pin_to_pocctrl()
3787 case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 28): in r8a779h0_pin_to_pocctrl()
3791 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12): in r8a779h0_pin_to_pocctrl()
3795 case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 13): in r8a779h0_pin_to_pocctrl()
3801 return 0; in r8a779h0_pin_to_pocctrl()
3805 return 0; in r8a779h0_pin_to_pocctrl()
3809 return 0; in r8a779h0_pin_to_pocctrl()
3812 return -EINVAL; in r8a779h0_pin_to_pocctrl()
3817 { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {
3818 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */
3819 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */
3820 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */
3821 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */
3822 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */
3823 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */
3824 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */
3825 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */
3826 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */
3827 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */
3828 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */
3829 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */
3830 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */
3831 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */
3832 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */
3833 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */
3834 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */
3835 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */
3836 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */
3851 { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {
3852 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */
3861 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */
3885 { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {
3886 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */
3895 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */
3919 { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {
3920 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */
3929 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */
3953 { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {
3954 [ 0] = RCAR_GP_PIN(4, 0), /* SCL0 */
3963 [ 9] = RCAR_GP_PIN(4, 9), /* HTX2 */
3987 { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {
3988 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */
3997 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */
4021 { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {
4022 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */
4031 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */
4055 { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {
4056 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */
4065 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */
4101 .unlock_reg = 0x1ff, /* PMMRn mask */