Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:f_
1 // SPDX-License-Identifier: GPL-2.0
3 * R8A779F0 processor support - PFC hardware block.
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
19 PORT_GP_CFG_21(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
29 * F_() : just information
34 #define GPSR0_20 F_(IRQ3, IP2SR0_19_16)
35 #define GPSR0_19 F_(IRQ2, IP2SR0_15_12)
36 #define GPSR0_18 F_(IRQ1, IP2SR0_11_8)
37 #define GPSR0_17 F_(IRQ0, IP2SR0_7_4)
38 #define GPSR0_16 F_(MSIOF0_SS2, IP2SR0_3_0)
39 #define GPSR0_15 F_(MSIOF0_SS1, IP1SR0_31_28)
40 #define GPSR0_14 F_(MSIOF0_SCK, IP1SR0_27_24)
41 #define GPSR0_13 F_(MSIOF0_TXD, IP1SR0_23_20)
42 #define GPSR0_12 F_(MSIOF0_RXD, IP1SR0_19_16)
43 #define GPSR0_11 F_(MSIOF0_SYNC, IP1SR0_15_12)
44 #define GPSR0_10 F_(CTS0_N, IP1SR0_11_8)
45 #define GPSR0_9 F_(RTS0_N, IP1SR0_7_4)
46 #define GPSR0_8 F_(SCK0, IP1SR0_3_0)
47 #define GPSR0_7 F_(TX0, IP0SR0_31_28)
48 #define GPSR0_6 F_(RX0, IP0SR0_27_24)
49 #define GPSR0_5 F_(HRTS0_N, IP0SR0_23_20)
50 #define GPSR0_4 F_(HCTS0_N, IP0SR0_19_16)
51 #define GPSR0_3 F_(HTX0, IP0SR0_15_12)
52 #define GPSR0_2 F_(HRX0, IP0SR0_11_8)
53 #define GPSR0_1 F_(HSCK0, IP0SR0_7_4)
54 #define GPSR0_0 F_(SCIF_CLK, IP0SR0_3_0)
74 #define GPSR1_7 F_(GP1_07, IP0SR1_31_28)
75 #define GPSR1_6 F_(GP1_06, IP0SR1_27_24)
76 #define GPSR1_5 F_(GP1_05, IP0SR1_23_20)
77 #define GPSR1_4 F_(GP1_04, IP0SR1_19_16)
78 #define GPSR1_3 F_(GP1_03, IP0SR1_15_12)
79 #define GPSR1_2 F_(GP1_02, IP0SR1_11_8)
80 #define GPSR1_1 F_(GP1_01, IP0SR1_7_4)
81 #define GPSR1_0 F_(GP1_00, IP0SR1_3_0)
123 /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
124 …_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
125 …OF3_SCK) F_(0, 0) F_(0, 0) FM(TSN0_AVTP_CAPTURE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
126 …IOF3_RXD) F_(0, 0) F_(0, 0) FM(TSN0_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
127 … FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
128 …(MSIOF3_SS1) F_(0, 0) F_(0, 0) FM(TSN0_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
129 …(MSIOF3_SS2) F_(0, 0) F_(0, 0) FM(TSN0_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
130 …) F_(0, 0) FM(MSIOF1_RXD) F_(0, 0) FM(TSN1_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
131 … F_(0, 0) FM(MSIOF1_TXD) F_(0, 0) FM(TSN1_AVTP_CAPTURE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
132 /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
133 …(HSCK1) F_(0, 0) FM(MSIOF1_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
134 …MSIOF3_SYNC) F_(0, 0) F_(0, 0) FM(TSN1_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
135 …1_N) F_(0, 0) FM(MSIOF1_SYNC) F_(0, 0) FM(TSN1_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
136 …CTS1_N) FM(IRQ4) F_(0, 0) FM(TSN0_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
137 …HRX3) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
138 …HTX3) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
139 …SCK3) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
140 …RTS1_N) FM(IRQ5) F_(0, 0) FM(TSN1_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
141 /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
142 …2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
143 … F_(0, 0) F_(0, 0) FM(MSIOF1_SS1) F_(0, 0) FM(TSN0_MAGIC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
144 …F_(0, 0) F_(0, 0) FM(MSIOF1_SS2) F_(0, 0) FM(TSN0_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
145 …) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN1_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
146 …) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
148 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */
149 …LK1) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
150 …CLK4) FM(HRX2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
151 … F_(0, 0) FM(HTX2) FM(MSIOF2_SS1) F_(0, 0) FM(TSN2_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
152 …2) FM(CTS4_N) FM(TSN2_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
153 …M(MSIOF2_SYNC) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
154 …_SCK) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
155 …_RXD) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
156 …_TXD) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
205 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
206 #define MOD_SEL1_11_10 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
207 #define MOD_SEL1_9_8 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
208 #define MOD_SEL1_7_6 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
209 #define MOD_SEL1_5_4 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
210 #define MOD_SEL1_3_2 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
211 #define MOD_SEL1_1_0 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
227 PINMUX_RESERVED = 0,
233 #define F_(x, y) macro
241 #undef F_
244 #define F_(x, y) macro
252 #undef F_
257 /* Using GP_1_[0-9] requires disabling I2C in MOD_SEL1 */
481 PINMUX_IPSR_NOGM(0, GP1_08, SEL_I2C4_0),
485 PINMUX_IPSR_NOGM(0, GP1_09, SEL_I2C4_0),
489 PINMUX_IPSR_NOGM(0, GP1_10, SEL_I2C5_0),
493 PINMUX_IPSR_NOGM(0, GP1_11, SEL_I2C5_0),
498 * Pins not associated with a GPIO port.
509 /* - HSCIF0 ----------------------------------------------------------------- */
512 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
519 RCAR_GP_PIN(0, 1),
526 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
532 /* - HSCIF1 ----------------------------------------------------------------- */
535 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
542 RCAR_GP_PIN(0, 8),
549 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
555 /* - HSCIF2 ----------------------------------------------------------------- */
565 RCAR_GP_PIN(1, 0),
578 /* - HSCIF3 ----------------------------------------------------------------- */
581 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
588 RCAR_GP_PIN(0, 14),
595 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
601 /* - I2C0 ------------------------------------------------------------------- */
604 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
610 /* - I2C1 ------------------------------------------------------------------- */
619 /* - I2C2 ------------------------------------------------------------------- */
628 /* - I2C3 ------------------------------------------------------------------- */
637 /* - I2C4 ------------------------------------------------------------------- */
640 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
646 /* - I2C5 ------------------------------------------------------------------- */
656 /* - INTC-EX ---------------------------------------------------------------- */
659 RCAR_GP_PIN(0, 17),
666 RCAR_GP_PIN(0, 18),
673 RCAR_GP_PIN(0, 19),
680 RCAR_GP_PIN(0, 20),
687 RCAR_GP_PIN(0, 11),
694 RCAR_GP_PIN(0, 15),
700 /* - MMC -------------------------------------------------------------------- */
702 /* MMC_SD_D[0:3], MMC_D[4:7] */
743 /* - MSIOF0 ----------------------------------------------------------------- */
746 RCAR_GP_PIN(0, 14),
753 RCAR_GP_PIN(0, 11),
760 RCAR_GP_PIN(0, 15),
767 RCAR_GP_PIN(0, 16),
774 RCAR_GP_PIN(0, 13),
781 RCAR_GP_PIN(0, 12),
787 /* - MSIOF1 ----------------------------------------------------------------- */
790 RCAR_GP_PIN(0, 8),
797 RCAR_GP_PIN(0, 10),
804 RCAR_GP_PIN(0, 17),
811 RCAR_GP_PIN(0, 18),
818 RCAR_GP_PIN(0, 7),
825 RCAR_GP_PIN(0, 6),
831 /* - MSIOF2 ----------------------------------------------------------------- */
875 /* - MSIOF3 ----------------------------------------------------------------- */
878 RCAR_GP_PIN(0, 1),
885 RCAR_GP_PIN(0, 9),
892 RCAR_GP_PIN(0, 4),
899 RCAR_GP_PIN(0, 5),
906 RCAR_GP_PIN(0, 3),
913 RCAR_GP_PIN(0, 2),
919 /* - PCIE ------------------------------------------------------------------- */
938 /* - QSPI0 ------------------------------------------------------------------ */
948 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 12),
956 /* - QSPI1 ------------------------------------------------------------------ */
974 /* - SCIF0 ------------------------------------------------------------------ */
977 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
984 RCAR_GP_PIN(0, 8),
991 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
997 /* - SCIF1 ------------------------------------------------------------------ */
1000 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1007 RCAR_GP_PIN(0, 14),
1014 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1020 /* - SCIF3 ------------------------------------------------------------------ */
1023 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1030 RCAR_GP_PIN(0, 1),
1037 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
1043 /* - SCIF4 ------------------------------------------------------------------ */
1066 /* - SCIF Clock ------------------------------------------------------------- */
1069 RCAR_GP_PIN(0, 0),
1075 /* - TSN0 ------------------------------------------------ */
1078 RCAR_GP_PIN(0, 11),
1085 RCAR_GP_PIN(0, 17),
1092 RCAR_GP_PIN(0, 18),
1099 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1141 RCAR_GP_PIN(0, 1),
1148 RCAR_GP_PIN(0, 2),
1168 /* - TSN1 ------------------------------------------------ */
1171 RCAR_GP_PIN(0, 15),
1178 RCAR_GP_PIN(0, 19),
1185 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1206 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
1220 RCAR_GP_PIN(0, 7),
1227 RCAR_GP_PIN(0, 6),
1247 /* - TSN2 ------------------------------------------------ */
1250 RCAR_GP_PIN(0, 16),
1257 RCAR_GP_PIN(0, 20),
1278 RCAR_GP_PIN(3, 9),
1618 #define F_(x, y) FN_##y macro
1620 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6050040, 32,
1621 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1647 { PINMUX_CFG_REG_VAR("GPSR1", 0xe6050840, 32,
1648 GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1678 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6051040, 32,
1679 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1701 { PINMUX_CFG_REG_VAR("GPSR3", 0xe6051840, 32,
1702 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1726 #undef F_
1729 #define F_(x, y) x, macro
1731 { PINMUX_CFG_REG("IP0SR0", 0xe6050060, 32, 4, GROUP(
1741 { PINMUX_CFG_REG("IP1SR0", 0xe6050064, 32, 4, GROUP(
1751 { PINMUX_CFG_REG_VAR("IP2SR0", 0xe6050068, 32,
1752 GROUP(-12, 4, 4, 4, 4, 4),
1761 { PINMUX_CFG_REG("IP0SR1", 0xe6050860, 32, 4, GROUP(
1771 #undef F_
1774 #define F_(x, y) x, macro
1776 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6050900, 32,
1777 GROUP(-20, 2, 2, 2, 2, 2, 2),
1779 /* RESERVED 31-12 */
1791 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6050080) {
1792 { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */
1793 { RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */
1794 { RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */
1795 { RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */
1796 { RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */
1797 { RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */
1798 { RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */
1799 { RCAR_GP_PIN(0, 0), 0, 3 }, /* SCIF_CLK */
1801 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6050084) {
1802 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */
1803 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */
1804 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF0_TXD */
1805 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */
1806 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF0_SYNC */
1807 { RCAR_GP_PIN(0, 10), 8, 3 }, /* CTS0_N */
1808 { RCAR_GP_PIN(0, 9), 4, 3 }, /* RTS0_N */
1809 { RCAR_GP_PIN(0, 8), 0, 3 }, /* SCK0 */
1811 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6050088) {
1812 { RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */
1813 { RCAR_GP_PIN(0, 19), 12, 3 }, /* IRQ2 */
1814 { RCAR_GP_PIN(0, 18), 8, 3 }, /* IRQ1 */
1815 { RCAR_GP_PIN(0, 17), 4, 3 }, /* IRQ0 */
1816 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF0_SS2 */
1818 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050880) {
1826 { RCAR_GP_PIN(1, 0), 0, 3 }, /* GP1_00 */
1828 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050884) {
1835 { RCAR_GP_PIN(1, 9), 4, 3 }, /* GP1_09 */
1836 { RCAR_GP_PIN(1, 8), 0, 3 }, /* GP1_08 */
1838 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050888) {
1846 { RCAR_GP_PIN(1, 16), 0, 3 }, /* MMC_SD_D3 */
1848 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605088c) {
1849 { RCAR_GP_PIN(1, 24), 0, 3 }, /* SD_WP */
1851 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6051080) {
1859 { RCAR_GP_PIN(2, 0), 0, 2 }, /* RPC_INT_N */
1861 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6051084) {
1868 { RCAR_GP_PIN(2, 9), 4, 2 }, /* QSPI0_MOSI_IO0 */
1869 { RCAR_GP_PIN(2, 8), 0, 2 }, /* QSPI1_SPCLK */
1871 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6051088) {
1872 { RCAR_GP_PIN(2, 16), 0, 3 }, /* PCIE1_CLKREQ_N */
1874 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6051880) {
1882 { RCAR_GP_PIN(3, 0), 0, 3 }, /* TSN1_MDIO_B */
1884 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6051884) {
1891 { RCAR_GP_PIN(3, 9), 4, 3 }, /* TSN2_PHY_INT_B */
1892 { RCAR_GP_PIN(3, 8), 0, 3 }, /* TSN0_LINK_B */
1894 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6051888) {
1897 { RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */
1910 [POC0] = { 0xe60500a0, },
1911 [POC1] = { 0xe60508a0, },
1912 [POC3] = { 0xe60518a0, },
1913 [TD0SEL1] = { 0xe6050920, },
1919 int bit = pin & 0x1f; in r8a779f0_pin_to_pocctrl()
1922 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 20)) in r8a779f0_pin_to_pocctrl()
1926 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 24)) in r8a779f0_pin_to_pocctrl()
1930 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 18)) in r8a779f0_pin_to_pocctrl()
1933 return -EINVAL; in r8a779f0_pin_to_pocctrl()
1937 { PINMUX_BIAS_REG("PUEN0", 0xe60500c0, "PUD0", 0xe60500e0) {
1938 [ 0] = RCAR_GP_PIN(0, 0), /* SCIF_CLK */
1939 [ 1] = RCAR_GP_PIN(0, 1), /* HSCK0 */
1940 [ 2] = RCAR_GP_PIN(0, 2), /* HRX0 */
1941 [ 3] = RCAR_GP_PIN(0, 3), /* HTX0 */
1942 [ 4] = RCAR_GP_PIN(0, 4), /* HCTS0_N */
1943 [ 5] = RCAR_GP_PIN(0, 5), /* HRTS0_N */
1944 [ 6] = RCAR_GP_PIN(0, 6), /* RX0 */
1945 [ 7] = RCAR_GP_PIN(0, 7), /* TX0 */
1946 [ 8] = RCAR_GP_PIN(0, 8), /* SCK0 */
1947 [ 9] = RCAR_GP_PIN(0, 9), /* RTS0_N */
1948 [10] = RCAR_GP_PIN(0, 10), /* CTS0_N */
1949 [11] = RCAR_GP_PIN(0, 11), /* MSIOF0_SYNC */
1950 [12] = RCAR_GP_PIN(0, 12), /* MSIOF0_RXD */
1951 [13] = RCAR_GP_PIN(0, 13), /* MSIOF0_TXD */
1952 [14] = RCAR_GP_PIN(0, 14), /* MSIOF0_SCK */
1953 [15] = RCAR_GP_PIN(0, 15), /* MSIOF0_SS1 */
1954 [16] = RCAR_GP_PIN(0, 16), /* MSIOF0_SS2 */
1955 [17] = RCAR_GP_PIN(0, 17), /* IRQ0 */
1956 [18] = RCAR_GP_PIN(0, 18), /* IRQ1 */
1957 [19] = RCAR_GP_PIN(0, 19), /* IRQ2 */
1958 [20] = RCAR_GP_PIN(0, 20), /* IRQ3 */
1971 { PINMUX_BIAS_REG("PUEN1", 0xe60508c0, "PUD1", 0xe60508e0) {
1972 [ 0] = RCAR_GP_PIN(1, 0), /* GP1_00 */
1981 [ 9] = RCAR_GP_PIN(1, 9), /* GP1_09 */
2005 { PINMUX_BIAS_REG("PUEN2", 0xe60510c0, "PUD2", 0xe60510e0) {
2006 [ 0] = RCAR_GP_PIN(2, 0), /* RPC_INT_N */
2015 [ 9] = RCAR_GP_PIN(2, 9), /* QSPI0_MOSI_IO0 */
2039 { PINMUX_BIAS_REG("PUEN3", 0xe60518c0, "PUD3", 0xe60518e0) {
2040 [ 0] = RCAR_GP_PIN(3, 0), /* TSN1_MDIO_B */
2049 [ 9] = RCAR_GP_PIN(3, 9), /* TSN2_PHY_INT_B */
2085 .unlock_reg = 0x1ff, /* PMMRn mask */