Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:f_
1 // SPDX-License-Identifier: GPL-2.0
3 * R8A779A0 processor support - PFC hardware block.
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
19 PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \
20 PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
22 PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
23 PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
24 PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
25 PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
26 PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
27 PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
28 PORT_GP_CFG_1(0, 23, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
29 PORT_GP_CFG_1(0, 24, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
30 PORT_GP_CFG_1(0, 25, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
31 PORT_GP_CFG_1(0, 26, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
32 PORT_GP_CFG_1(0, 27, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
42 PORT_GP_CFG_1(2, 9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
85 PORT_GP_CFG_18(9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
86 PORT_GP_CFG_1(9, 18, fn, sfx, CFG_FLAGS), \
87 PORT_GP_CFG_1(9, 19, fn, sfx, CFG_FLAGS), \
88 PORT_GP_CFG_1(9, 20, fn, sfx, CFG_FLAGS)
99 * F_() : just information
134 #define GPSR1_30 F_(GP1_30, IP3SR1_27_24)
135 #define GPSR1_29 F_(GP1_29, IP3SR1_23_20)
136 #define GPSR1_28 F_(GP1_28, IP3SR1_19_16)
137 #define GPSR1_27 F_(IRQ3, IP3SR1_15_12)
138 #define GPSR1_26 F_(IRQ2, IP3SR1_11_8)
139 #define GPSR1_25 F_(IRQ1, IP3SR1_7_4)
140 #define GPSR1_24 F_(IRQ0, IP3SR1_3_0)
141 #define GPSR1_23 F_(MSIOF2_SS2, IP2SR1_31_28)
142 #define GPSR1_22 F_(MSIOF2_SS1, IP2SR1_27_24)
143 #define GPSR1_21 F_(MSIOF2_SYNC, IP2SR1_23_20)
144 #define GPSR1_20 F_(MSIOF2_SCK, IP2SR1_19_16)
145 #define GPSR1_19 F_(MSIOF2_TXD, IP2SR1_15_12)
146 #define GPSR1_18 F_(MSIOF2_RXD, IP2SR1_11_8)
147 #define GPSR1_17 F_(MSIOF1_SS2, IP2SR1_7_4)
148 #define GPSR1_16 F_(MSIOF1_SS1, IP2SR1_3_0)
149 #define GPSR1_15 F_(MSIOF1_SYNC, IP1SR1_31_28)
150 #define GPSR1_14 F_(MSIOF1_SCK, IP1SR1_27_24)
151 #define GPSR1_13 F_(MSIOF1_TXD, IP1SR1_23_20)
152 #define GPSR1_12 F_(MSIOF1_RXD, IP1SR1_19_16)
153 #define GPSR1_11 F_(MSIOF0_SS2, IP1SR1_15_12)
154 #define GPSR1_10 F_(MSIOF0_SS1, IP1SR1_11_8)
155 #define GPSR1_9 F_(MSIOF0_SYNC, IP1SR1_7_4)
156 #define GPSR1_8 F_(MSIOF0_SCK, IP1SR1_3_0)
157 #define GPSR1_7 F_(MSIOF0_TXD, IP0SR1_31_28)
158 #define GPSR1_6 F_(MSIOF0_RXD, IP0SR1_27_24)
159 #define GPSR1_5 F_(HTX0, IP0SR1_23_20)
160 #define GPSR1_4 F_(HCTS0_N, IP0SR1_19_16)
161 #define GPSR1_3 F_(HRTS0_N, IP0SR1_15_12)
162 #define GPSR1_2 F_(HSCK0, IP0SR1_11_8)
163 #define GPSR1_1 F_(HRX0, IP0SR1_7_4)
164 #define GPSR1_0 F_(SCIF_CLK, IP0SR1_3_0)
168 #define GPSR2_23 F_(TCLK1_A, IP2SR2_31_28)
169 #define GPSR2_22 F_(TPU0TO1, IP2SR2_27_24)
170 #define GPSR2_21 F_(TPU0TO0, IP2SR2_23_20)
171 #define GPSR2_20 F_(CLK_EXTFXR, IP2SR2_19_16)
172 #define GPSR2_19 F_(RXDB_EXTFXR, IP2SR2_15_12)
173 #define GPSR2_18 F_(FXR_TXDB, IP2SR2_11_8)
174 #define GPSR2_17 F_(RXDA_EXTFXR_A, IP2SR2_7_4)
175 #define GPSR2_16 F_(FXR_TXDA_A, IP2SR2_3_0)
176 #define GPSR2_15 F_(GP2_15, IP1SR2_31_28)
177 #define GPSR2_14 F_(GP2_14, IP1SR2_27_24)
178 #define GPSR2_13 F_(GP2_13, IP1SR2_23_20)
179 #define GPSR2_12 F_(GP2_12, IP1SR2_19_16)
180 #define GPSR2_11 F_(GP2_11, IP1SR2_15_12)
181 #define GPSR2_10 F_(GP2_10, IP1SR2_11_8)
182 #define GPSR2_9 F_(GP2_09, IP1SR2_7_4)
183 #define GPSR2_8 F_(GP2_08, IP1SR2_3_0)
184 #define GPSR2_7 F_(GP2_07, IP0SR2_31_28)
185 #define GPSR2_6 F_(GP2_06, IP0SR2_27_24)
186 #define GPSR2_5 F_(GP2_05, IP0SR2_23_20)
187 #define GPSR2_4 F_(GP2_04, IP0SR2_19_16)
188 #define GPSR2_3 F_(GP2_03, IP0SR2_15_12)
189 #define GPSR2_2 F_(GP2_02, IP0SR2_11_8)
190 #define GPSR2_1 F_(IPC_CLKOUT, IP0SR2_7_4)
191 #define GPSR2_0 F_(IPC_CLKIN, IP0SR2_3_0)
197 #define GPSR3_13 F_(CANFD6_TX, IP1SR3_23_20)
198 #define GPSR3_12 F_(CANFD5_RX, IP1SR3_19_16)
199 #define GPSR3_11 F_(CANFD5_TX, IP1SR3_15_12)
200 #define GPSR3_10 F_(CANFD4_RX, IP1SR3_11_8)
201 #define GPSR3_9 F_(CANFD4_TX, IP1SR3_7_4)
202 #define GPSR3_8 F_(CANFD3_RX, IP1SR3_3_0)
203 #define GPSR3_7 F_(CANFD3_TX, IP0SR3_31_28)
204 #define GPSR3_6 F_(CANFD2_RX, IP0SR3_27_24)
205 #define GPSR3_5 F_(CANFD2_TX, IP0SR3_23_20)
208 #define GPSR3_2 F_(CANFD0_RX, IP0SR3_11_8)
209 #define GPSR3_1 F_(CANFD0_TX, IP0SR3_7_4)
219 #define GPSR4_20 F_(AVB0_AVTP_PPS, IP2SR4_19_16)
220 #define GPSR4_19 F_(AVB0_AVTP_CAPTURE, IP2SR4_15_12)
221 #define GPSR4_18 F_(AVB0_AVTP_MATCH, IP2SR4_11_8)
222 #define GPSR4_17 F_(AVB0_LINK, IP2SR4_7_4)
224 #define GPSR4_15 F_(AVB0_MAGIC, IP1SR4_31_28)
225 #define GPSR4_14 F_(AVB0_MDC, IP1SR4_27_24)
226 #define GPSR4_13 F_(AVB0_MDIO, IP1SR4_23_20)
227 #define GPSR4_12 F_(AVB0_TXCREFCLK, IP1SR4_19_16)
228 #define GPSR4_11 F_(AVB0_TD3, IP1SR4_15_12)
229 #define GPSR4_10 F_(AVB0_TD2, IP1SR4_11_8)
230 #define GPSR4_9 F_(AVB0_TD1, IP1SR4_7_4)
231 #define GPSR4_8 F_(AVB0_TD0, IP1SR4_3_0)
232 #define GPSR4_7 F_(AVB0_TXC, IP0SR4_31_28)
233 #define GPSR4_6 F_(AVB0_TX_CTL, IP0SR4_27_24)
234 #define GPSR4_5 F_(AVB0_RD3, IP0SR4_23_20)
235 #define GPSR4_4 F_(AVB0_RD2, IP0SR4_19_16)
236 #define GPSR4_3 F_(AVB0_RD1, IP0SR4_15_12)
237 #define GPSR4_2 F_(AVB0_RD0, IP0SR4_11_8)
238 #define GPSR4_1 F_(AVB0_RXC, IP0SR4_7_4)
239 #define GPSR4_0 F_(AVB0_RX_CTL, IP0SR4_3_0)
242 #define GPSR5_20 F_(AVB1_AVTP_PPS, IP2SR5_19_16)
243 #define GPSR5_19 F_(AVB1_AVTP_CAPTURE, IP2SR5_15_12)
244 #define GPSR5_18 F_(AVB1_AVTP_MATCH, IP2SR5_11_8)
245 #define GPSR5_17 F_(AVB1_LINK, IP2SR5_7_4)
247 #define GPSR5_15 F_(AVB1_MAGIC, IP1SR5_31_28)
248 #define GPSR5_14 F_(AVB1_MDC, IP1SR5_27_24)
249 #define GPSR5_13 F_(AVB1_MDIO, IP1SR5_23_20)
250 #define GPSR5_12 F_(AVB1_TXCREFCLK, IP1SR5_19_16)
251 #define GPSR5_11 F_(AVB1_TD3, IP1SR5_15_12)
252 #define GPSR5_10 F_(AVB1_TD2, IP1SR5_11_8)
253 #define GPSR5_9 F_(AVB1_TD1, IP1SR5_7_4)
254 #define GPSR5_8 F_(AVB1_TD0, IP1SR5_3_0)
255 #define GPSR5_7 F_(AVB1_TXC, IP0SR5_31_28)
256 #define GPSR5_6 F_(AVB1_TX_CTL, IP0SR5_27_24)
257 #define GPSR5_5 F_(AVB1_RD3, IP0SR5_23_20)
258 #define GPSR5_4 F_(AVB1_RD2, IP0SR5_19_16)
259 #define GPSR5_3 F_(AVB1_RD1, IP0SR5_15_12)
260 #define GPSR5_2 F_(AVB1_RD0, IP0SR5_11_8)
261 #define GPSR5_1 F_(AVB1_RXC, IP0SR5_7_4)
262 #define GPSR5_0 F_(AVB1_RX_CTL, IP0SR5_3_0)
356 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
357 …SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
358 …HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
359 …SCK0) FM(SCK0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
360 …_N) FM(RTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
361 …_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
362 …HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
363 …OF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
364 …OF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR3) FM(A7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
365 /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
366 …OF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR4) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
367 …F0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
368 …OF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
369 …OF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR7) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
370 …OF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DG2) FM(A12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
371 …FM(HRX3) FM(SCK3) F_(0, 0) FM(DU_DG3) FM(A13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
372 …HSCK3) FM(CTS3_N) F_(0, 0) FM(DU_DG4) FM(A14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
373 …TS3_N) FM(RTS3_N) F_(0, 0) FM(DU_DG5) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
374 /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
375 …HCTS3_N) FM(RX3) F_(0, 0) FM(DU_DG6) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
376 …FM(HTX3) FM(TX3) F_(0, 0) FM(DU_DG7) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
377 …M(HSCK1) FM(SCK1) F_(0, 0) FM(DU_DB2) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
378 …TS1_N) FM(CTS1_N) F_(0, 0) FM(DU_DB3) FM(A19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
379 …TS1_N) FM(RTS1_N) F_(0, 0) FM(DU_DB4) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
380 …M(HRX1) FM(RX1_A) F_(0, 0) FM(DU_DB5) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
381 …M(HTX1) FM(TX1_A) F_(0, 0) FM(DU_DB6) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
382 … FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(DU_DB7) FM(A23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
384 /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
385 …RQ0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKOUT) FM(A24) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
386 …IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_HSYNC) FM(A25) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
387 …Q2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_VSYNC) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
388 …) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_ODDF_DISP_CDE) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
389 …(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
390 …(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
391 …(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
393 /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
394 …_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
395 …PC_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
396 …(GP2_02) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
397 …(GP2_03) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
398 …2_04) F_(0, 0) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) FM(D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
399 …FM(MSIOF4_TXD) FM(SCK4) F_(0, 0) FM(D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
400 …(MSIOF4_SCK) FM(CTS4_N) F_(0, 0) FM(D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
401 …MSIOF4_SYNC) FM(RTS4_N) F_(0, 0) FM(D8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
402 /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
403 …FM(MSIOF4_SS1) FM(RX4) F_(0, 0) FM(D9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
404 …M(MSIOF4_SS2) FM(TX4) F_(0, 0) FM(D10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
405 …B) FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) FM(D11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
406 …3) FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) FM(D12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
407 …4) FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) FM(D13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
408 …_13) F_(0, 0) FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
409 …4) FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
410 …5_SS2) FM(CPG_CPCKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
411 /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
412 …(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
413 …(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(BS_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
414 …(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
415 …(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
416 …(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
417 …SIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_WR_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
418 …U0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
419 …K1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
421 /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
422 …XDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
423 …TFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
424 …PU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
425 …PU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
426 …NFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
427 /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
428 …NFD3_RX) F_(0, 0) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
429 …_TX) F_(0, 0) FM(PWM4) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
430 …_RX) F_(0, 0) F_(0, 0) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
431 …_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
432 …_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
433 …_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
435 /* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
436 …B0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
437 …AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
438 …AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
439 …AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
440 …AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
441 …AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
442 …B0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
443 …AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
444 /* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
445 …AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
446 …AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
447 …AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
448 …AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
449 …CREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
450 …0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
451 …B0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
452 …_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
453 /* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
454 …B0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
455 …ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
456 …AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
457 …AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
459 /* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
460 …B1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
461 …AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
462 …AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
463 …AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
464 …AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
465 …AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
466 …B1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
467 …AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
468 /* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
469 …AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
470 …AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
471 …AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
472 …AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
473 …CREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
474 …1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
475 …B1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
476 …_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
477 /* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
478 …B1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
479 …B1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
480 …AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
481 …AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
564 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
565 #define MOD_SEL2_15_14 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3)
566 #define MOD_SEL2_13_12 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
567 #define MOD_SEL2_11_10 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
568 #define MOD_SEL2_9_8 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
569 #define MOD_SEL2_7_6 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
570 #define MOD_SEL2_5_4 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
571 #define MOD_SEL2_3_2 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
588 PINMUX_RESERVED = 0,
594 #define F_(x, y) macro
602 #undef F_
605 #define F_(x, y) macro
613 #undef F_
618 /* Using GP_2_[2-15] requires disabling I2C in MOD_SEL2 */
1231 * Pins not associated with a GPIO port.
1242 /* - AVB0 ------------------------------------------------ */
1277 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1279 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1318 /* - AVB1 ------------------------------------------------ */
1353 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1355 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
1394 /* - AVB2 ------------------------------------------------ */
1429 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1431 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
1470 /* - AVB3 ------------------------------------------------ */
1505 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1507 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1),
1546 /* - AVB4 ------------------------------------------------ */
1581 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1583 RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1),
1622 /* - AVB5 ------------------------------------------------ */
1625 RCAR_GP_PIN(9, 17),
1632 RCAR_GP_PIN(9, 15),
1639 RCAR_GP_PIN(9, 16),
1646 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13),
1656 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1657 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1658 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1659 RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1),
1660 RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1661 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1671 RCAR_GP_PIN(9, 12),
1678 RCAR_GP_PIN(9, 20),
1685 RCAR_GP_PIN(9, 19),
1692 RCAR_GP_PIN(9, 18),
1698 /* - CANFD0 ----------------------------------------------------------------- */
1707 /* - CANFD1 ----------------------------------------------------------------- */
1716 /* - CANFD2 ----------------------------------------------------------------- */
1725 /* - CANFD3 ----------------------------------------------------------------- */
1734 /* - CANFD4 ----------------------------------------------------------------- */
1737 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1743 /* - CANFD5 ----------------------------------------------------------------- */
1752 /* - CANFD6 ----------------------------------------------------------------- */
1761 /* - CANFD7 ----------------------------------------------------------------- */
1770 /* - CANFD Clock ------------------------------------------------------------ */
1773 RCAR_GP_PIN(3, 0),
1779 /* - DU --------------------------------------------------------------------- */
1782 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1819 /* - HSCIF0 ----------------------------------------------------------------- */
1842 /* - HSCIF1 ----------------------------------------------------------------- */
1865 /* - HSCIF2 ----------------------------------------------------------------- */
1868 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1888 /* - HSCIF3 ----------------------------------------------------------------- */
1911 /* - I2C0 ------------------------------------------------------------------- */
1920 /* - I2C1 ------------------------------------------------------------------- */
1929 /* - I2C2 ------------------------------------------------------------------- */
1938 /* - I2C3 ------------------------------------------------------------------- */
1941 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
1947 /* - I2C4 ------------------------------------------------------------------- */
1956 /* - I2C5 ------------------------------------------------------------------- */
1965 /* - I2C6 ------------------------------------------------------------------- */
1974 /* - INTC-EX ---------------------------------------------------------------- */
2018 /* - MMC -------------------------------------------------------------------- */
2020 /* MMC_SD_D[0:3], MMC_D[4:7] */
2021 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
2022 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
2023 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2024 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27),
2034 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 18),
2041 RCAR_GP_PIN(0, 16),
2048 RCAR_GP_PIN(0, 15),
2055 RCAR_GP_PIN(0, 17),
2061 /* - MSIOF0 ----------------------------------------------------------------- */
2071 RCAR_GP_PIN(1, 9),
2105 /* - MSIOF1 ----------------------------------------------------------------- */
2149 /* - MSIOF2 ----------------------------------------------------------------- */
2193 /* - MSIOF3 ----------------------------------------------------------------- */
2237 /* - MSIOF4 ----------------------------------------------------------------- */
2261 RCAR_GP_PIN(2, 9),
2281 /* - MSIOF5 ----------------------------------------------------------------- */
2325 /* - PWM0 ------------------------------------------------------------------- */
2334 /* - PWM1 ------------------------------------------------------------------- */
2343 /* - PWM2 ------------------------------------------------------------------- */
2352 /* - PWM3 ------------------------------------------------------------------- */
2361 /* - PWM4 ------------------------------------------------------------------- */
2364 RCAR_GP_PIN(3, 9),
2370 /* - QSPI0 ------------------------------------------------------------------ */
2373 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5),
2380 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2381 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2388 /* - QSPI1 ------------------------------------------------------------------ */
2391 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11),
2398 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
2399 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2406 /* - SCIF0 ------------------------------------------------------------------ */
2429 /* - SCIF1 ------------------------------------------------------------------ */
2459 /* - SCIF3 ------------------------------------------------------------------ */
2482 /* - SCIF4 ------------------------------------------------------------------ */
2485 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2505 /* - SCIF Clock ------------------------------------------------------------- */
2508 RCAR_GP_PIN(1, 0),
2514 /* - TMU -------------------------------------------------------------------- */
2561 /* - TPU ------------------------------------------------------------------- */
3163 #define F_(x, y) FN_##y macro
3165 { PINMUX_CFG_REG("GPSR0", 0xe6058040, 32, 1, GROUP(
3166 0, 0,
3167 0, 0,
3168 0, 0,
3169 0, 0,
3199 { PINMUX_CFG_REG("GPSR1", 0xe6050040, 32, 1, GROUP(
3200 0, 0,
3233 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6050840, 32,
3234 GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3264 { PINMUX_CFG_REG_VAR("GPSR3", 0xe6058840, 32,
3265 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3287 { PINMUX_CFG_REG("GPSR4", 0xe6060040, 32, 1, GROUP(
3288 0, 0,
3289 0, 0,
3290 0, 0,
3291 0, 0,
3292 0, 0,
3321 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060840, 32,
3322 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3348 { PINMUX_CFG_REG_VAR("GPSR6", 0xe6068040, 32,
3349 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3375 { PINMUX_CFG_REG_VAR("GPSR7", 0xe6068840, 32,
3376 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3402 { PINMUX_CFG_REG_VAR("GPSR8", 0xe6069040, 32,
3403 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3429 { PINMUX_CFG_REG_VAR("GPSR9", 0xe6069840, 32,
3430 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3456 #undef F_
3459 #define F_(x, y) x, macro
3461 { PINMUX_CFG_REG("IP0SR1", 0xe6050060, 32, 4, GROUP(
3471 { PINMUX_CFG_REG("IP1SR1", 0xe6050064, 32, 4, GROUP(
3481 { PINMUX_CFG_REG("IP2SR1", 0xe6050068, 32, 4, GROUP(
3491 { PINMUX_CFG_REG_VAR("IP3SR1", 0xe605006c, 32,
3492 GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
3503 { PINMUX_CFG_REG("IP0SR2", 0xe6050860, 32, 4, GROUP(
3513 { PINMUX_CFG_REG("IP1SR2", 0xe6050864, 32, 4, GROUP(
3523 { PINMUX_CFG_REG("IP2SR2", 0xe6050868, 32, 4, GROUP(
3533 { PINMUX_CFG_REG_VAR("IP0SR3", 0xe6058860, 32,
3534 GROUP(4, 4, 4, -8, 4, 4, -4),
3544 { PINMUX_CFG_REG_VAR("IP1SR3", 0xe6058864, 32,
3545 GROUP(-8, 4, 4, 4, 4, 4, 4),
3555 { PINMUX_CFG_REG("IP0SR4", 0xe6060060, 32, 4, GROUP(
3565 { PINMUX_CFG_REG("IP1SR4", 0xe6060064, 32, 4, GROUP(
3575 { PINMUX_CFG_REG_VAR("IP2SR4", 0xe6060068, 32,
3576 GROUP(-12, 4, 4, 4, 4, -4),
3585 { PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP(
3595 { PINMUX_CFG_REG("IP1SR5", 0xe6060864, 32, 4, GROUP(
3605 { PINMUX_CFG_REG_VAR("IP2SR5", 0xe6060868, 32,
3606 GROUP(-12, 4, 4, 4, 4, -4),
3615 #undef F_
3618 #define F_(x, y) x, macro
3620 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32,
3621 GROUP(-16, 2, 2, 2, 2, 2, 2, 2, -2),
3623 /* RESERVED 31-16 */
3631 /* RESERVED 1-0 */ ))
3637 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6058080) {
3638 { RCAR_GP_PIN(0, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
3639 { RCAR_GP_PIN(0, 6), 24, 2 }, /* QSPI1_SPCLK */
3640 { RCAR_GP_PIN(0, 5), 20, 2 }, /* QSPI0_SSL */
3641 { RCAR_GP_PIN(0, 4), 16, 2 }, /* QSPI0_IO3 */
3642 { RCAR_GP_PIN(0, 3), 12, 2 }, /* QSPI0_IO2 */
3643 { RCAR_GP_PIN(0, 2), 8, 2 }, /* QSPI0_MISO_IO1 */
3644 { RCAR_GP_PIN(0, 1), 4, 2 }, /* QSPI0_MOSI_IO0 */
3645 { RCAR_GP_PIN(0, 0), 0, 2 }, /* QSPI0_SPCLK */
3647 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6058084) {
3648 { RCAR_GP_PIN(0, 15), 28, 3 }, /* SD_WP */
3649 { RCAR_GP_PIN(0, 14), 24, 2 }, /* RPC_INT_N */
3650 { RCAR_GP_PIN(0, 13), 20, 2 }, /* RPC_WP_N */
3651 { RCAR_GP_PIN(0, 12), 16, 2 }, /* RPC_RESET_N */
3652 { RCAR_GP_PIN(0, 11), 12, 2 }, /* QSPI1_SSL */
3653 { RCAR_GP_PIN(0, 10), 8, 2 }, /* QSPI1_IO3 */
3654 { RCAR_GP_PIN(0, 9), 4, 2 }, /* QSPI1_IO2 */
3655 { RCAR_GP_PIN(0, 8), 0, 2 }, /* QSPI1_MISO_IO1 */
3657 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6058088) {
3658 { RCAR_GP_PIN(0, 23), 28, 3 }, /* MMC_SD_CLK */
3659 { RCAR_GP_PIN(0, 22), 24, 3 }, /* MMC_SD_D3 */
3660 { RCAR_GP_PIN(0, 21), 20, 3 }, /* MMC_SD_D2 */
3661 { RCAR_GP_PIN(0, 20), 16, 3 }, /* MMC_SD_D1 */
3662 { RCAR_GP_PIN(0, 19), 12, 3 }, /* MMC_SD_D0 */
3663 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MMC_SD_CMD */
3664 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MMC_DS */
3665 { RCAR_GP_PIN(0, 16), 0, 3 }, /* SD_CD */
3667 { PINMUX_DRIVE_REG("DRV3CTRL0", 0xe605808c) {
3668 { RCAR_GP_PIN(0, 27), 12, 3 }, /* MMC_D7 */
3669 { RCAR_GP_PIN(0, 26), 8, 3 }, /* MMC_D6 */
3670 { RCAR_GP_PIN(0, 25), 4, 3 }, /* MMC_D5 */
3671 { RCAR_GP_PIN(0, 24), 0, 3 }, /* MMC_D4 */
3673 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050080) {
3681 { RCAR_GP_PIN(1, 0), 0, 3 }, /* SCIF_CLK */
3683 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050084) {
3690 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_SYNC */
3691 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SCK */
3693 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050088) {
3701 { RCAR_GP_PIN(1, 16), 0, 3 }, /* MSIOF1_SS1 */
3703 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605008c) {
3710 { RCAR_GP_PIN(1, 24), 0, 3 }, /* IRQ0 */
3712 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6050880) {
3720 { RCAR_GP_PIN(2, 0), 0, 2 }, /* IPC_CLKIN */
3722 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6050884) {
3729 { RCAR_GP_PIN(2, 9), 4, 3 }, /* GP2_9 */
3730 { RCAR_GP_PIN(2, 8), 0, 3 }, /* GP2_8 */
3732 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6050888) {
3740 { RCAR_GP_PIN(2, 16), 0, 3 }, /* FXR_TXDA_A */
3742 { PINMUX_DRIVE_REG("DRV3CTRL2", 0xe605088c) {
3743 { RCAR_GP_PIN(2, 24), 0, 3 }, /* TCLK2_A */
3745 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6058880) {
3753 { RCAR_GP_PIN(3, 0), 0, 2 }, /* CAN_CLK */
3755 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6058884) {
3762 { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX */
3763 { RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */
3765 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) {
3766 { RCAR_GP_PIN(3, 16), 0, 3 }, /* CANFD7_RX */
3768 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xe6060080) {
3776 { RCAR_GP_PIN(4, 0), 0, 3 }, /* AVB0_RX_CTL */
3778 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xe6060084) {
3785 { RCAR_GP_PIN(4, 9), 4, 3 }, /* AVB0_TD1*/
3786 { RCAR_GP_PIN(4, 8), 0, 3 }, /* AVB0_TD0 */
3788 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xe6060088) {
3796 { RCAR_GP_PIN(4, 16), 0, 3 }, /* AVB0_PHY_INT */
3798 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xe606008c) {
3801 { RCAR_GP_PIN(4, 24), 0, 3 }, /* PCIE3_CLKREQ_N */
3803 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xe6060880) {
3811 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB1_RX_CTL */
3813 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xe6060884) {
3820 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB1_TD1*/
3821 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB1_TD0 */
3823 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xe6060888) {
3828 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB1_PHY_INT */
3830 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xe6068080) {
3838 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB2_RX_CTL */
3840 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xe6068084) {
3847 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB2_TD1*/
3848 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB2_TD0 */
3850 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xe6068088) {
3855 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB2_PHY_INT */
3857 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xe6068880) {
3865 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB3_RX_CTL */
3867 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xe6068884) {
3874 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB3_TD1*/
3875 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB3_TD0 */
3877 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xe6068888) {
3882 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB3_PHY_INT */
3884 { PINMUX_DRIVE_REG("DRV0CTRL8", 0xe6069080) {
3892 { RCAR_GP_PIN(8, 0), 0, 3 }, /* AVB4_RX_CTL */
3894 { PINMUX_DRIVE_REG("DRV1CTRL8", 0xe6069084) {
3901 { RCAR_GP_PIN(8, 9), 4, 3 }, /* AVB4_TD1*/
3902 { RCAR_GP_PIN(8, 8), 0, 3 }, /* AVB4_TD0 */
3904 { PINMUX_DRIVE_REG("DRV2CTRL8", 0xe6069088) {
3909 { RCAR_GP_PIN(8, 16), 0, 3 }, /* AVB4_PHY_INT */
3911 { PINMUX_DRIVE_REG("DRV0CTRL9", 0xe6069880) {
3912 { RCAR_GP_PIN(9, 7), 28, 3 }, /* AVB5_TXC */
3913 { RCAR_GP_PIN(9, 6), 24, 3 }, /* AVB5_TX_CTL */
3914 { RCAR_GP_PIN(9, 5), 20, 3 }, /* AVB5_RD3 */
3915 { RCAR_GP_PIN(9, 4), 16, 3 }, /* AVB5_RD2 */
3916 { RCAR_GP_PIN(9, 3), 12, 3 }, /* AVB5_RD1 */
3917 { RCAR_GP_PIN(9, 2), 8, 3 }, /* AVB5_RD0 */
3918 { RCAR_GP_PIN(9, 1), 4, 3 }, /* AVB5_RXC */
3919 { RCAR_GP_PIN(9, 0), 0, 3 }, /* AVB5_RX_CTL */
3921 { PINMUX_DRIVE_REG("DRV1CTRL9", 0xe6069884) {
3922 { RCAR_GP_PIN(9, 15), 28, 3 }, /* AVB5_MAGIC */
3923 { RCAR_GP_PIN(9, 14), 24, 3 }, /* AVB5_MDC */
3924 { RCAR_GP_PIN(9, 13), 20, 3 }, /* AVB5_MDIO */
3925 { RCAR_GP_PIN(9, 12), 16, 3 }, /* AVB5_TXCREFCLK */
3926 { RCAR_GP_PIN(9, 11), 12, 3 }, /* AVB5_TD3 */
3927 { RCAR_GP_PIN(9, 10), 8, 3 }, /* AVB5_TD2 */
3928 { RCAR_GP_PIN(9, 9), 4, 3 }, /* AVB5_TD1*/
3929 { RCAR_GP_PIN(9, 8), 0, 3 }, /* AVB5_TD0 */
3931 { PINMUX_DRIVE_REG("DRV2CTRL9", 0xe6069888) {
3932 { RCAR_GP_PIN(9, 20), 16, 3 }, /* AVB5_AVTP_PPS */
3933 { RCAR_GP_PIN(9, 19), 12, 3 }, /* AVB5_AVTP_CAPTURE */
3934 { RCAR_GP_PIN(9, 18), 8, 3 }, /* AVB5_AVTP_MATCH */
3935 { RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */
3936 { RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */
3955 [POC0] = { 0xe60580a0, },
3956 [POC1] = { 0xe60500a0, },
3957 [POC2] = { 0xe60508a0, },
3958 [POC4] = { 0xe60600a0, },
3959 [POC5] = { 0xe60608a0, },
3960 [POC6] = { 0xe60680a0, },
3961 [POC7] = { 0xe60688a0, },
3962 [POC8] = { 0xe60690a0, },
3963 [POC9] = { 0xe60698a0, },
3964 [TD1SEL0] = { 0xe6058124, },
3970 int bit = pin & 0x1f; in r8a779a0_pin_to_pocctrl()
3973 if (pin >= RCAR_GP_PIN(0, 15) && pin <= RCAR_GP_PIN(0, 27)) in r8a779a0_pin_to_pocctrl()
3977 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 30)) in r8a779a0_pin_to_pocctrl()
3985 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) in r8a779a0_pin_to_pocctrl()
3989 if (pin >= RCAR_GP_PIN(5, 0) && pin <= RCAR_GP_PIN(5, 17)) in r8a779a0_pin_to_pocctrl()
3993 if (pin >= RCAR_GP_PIN(6, 0) && pin <= RCAR_GP_PIN(6, 17)) in r8a779a0_pin_to_pocctrl()
3997 if (pin >= RCAR_GP_PIN(7, 0) && pin <= RCAR_GP_PIN(7, 17)) in r8a779a0_pin_to_pocctrl()
4001 if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 17)) in r8a779a0_pin_to_pocctrl()
4005 if (pin >= RCAR_GP_PIN(9, 0) && pin <= RCAR_GP_PIN(9, 17)) in r8a779a0_pin_to_pocctrl()
4008 return -EINVAL; in r8a779a0_pin_to_pocctrl()
4012 { PINMUX_BIAS_REG("PUEN0", 0xe60580c0, "PUD0", 0xe60580e0) {
4013 [ 0] = RCAR_GP_PIN(0, 0), /* QSPI0_SPCLK */
4014 [ 1] = RCAR_GP_PIN(0, 1), /* QSPI0_MOSI_IO0 */
4015 [ 2] = RCAR_GP_PIN(0, 2), /* QSPI0_MISO_IO1 */
4016 [ 3] = RCAR_GP_PIN(0, 3), /* QSPI0_IO2 */
4017 [ 4] = RCAR_GP_PIN(0, 4), /* QSPI0_IO3 */
4018 [ 5] = RCAR_GP_PIN(0, 5), /* QSPI0_SSL */
4019 [ 6] = RCAR_GP_PIN(0, 6), /* QSPI1_SPCLK */
4020 [ 7] = RCAR_GP_PIN(0, 7), /* QSPI1_MOSI_IO0 */
4021 [ 8] = RCAR_GP_PIN(0, 8), /* QSPI1_MISO_IO1 */
4022 [ 9] = RCAR_GP_PIN(0, 9), /* QSPI1_IO2 */
4023 [10] = RCAR_GP_PIN(0, 10), /* QSPI1_IO3 */
4024 [11] = RCAR_GP_PIN(0, 11), /* QSPI1_SSL */
4025 [12] = RCAR_GP_PIN(0, 12), /* RPC_RESET_N */
4026 [13] = RCAR_GP_PIN(0, 13), /* RPC_WP_N */
4027 [14] = RCAR_GP_PIN(0, 14), /* RPC_INT_N */
4028 [15] = RCAR_GP_PIN(0, 15), /* SD_WP */
4029 [16] = RCAR_GP_PIN(0, 16), /* SD_CD */
4030 [17] = RCAR_GP_PIN(0, 17), /* MMC_DS */
4031 [18] = RCAR_GP_PIN(0, 18), /* MMC_SD_CMD */
4032 [19] = RCAR_GP_PIN(0, 19), /* MMC_SD_D0 */
4033 [20] = RCAR_GP_PIN(0, 20), /* MMC_SD_D1 */
4034 [21] = RCAR_GP_PIN(0, 21), /* MMC_SD_D2 */
4035 [22] = RCAR_GP_PIN(0, 22), /* MMC_SD_D3 */
4036 [23] = RCAR_GP_PIN(0, 23), /* MMC_SD_CLK */
4037 [24] = RCAR_GP_PIN(0, 24), /* MMC_D4 */
4038 [25] = RCAR_GP_PIN(0, 25), /* MMC_D5 */
4039 [26] = RCAR_GP_PIN(0, 26), /* MMC_D6 */
4040 [27] = RCAR_GP_PIN(0, 27), /* MMC_D7 */
4046 { PINMUX_BIAS_REG("PUEN1", 0xe60500c0, "PUD1", 0xe60500e0) {
4047 [ 0] = RCAR_GP_PIN(1, 0), /* SCIF_CLK */
4056 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_SYNC */
4080 { PINMUX_BIAS_REG("PUEN2", 0xe60508c0, "PUD2", 0xe60508e0) {
4081 [ 0] = RCAR_GP_PIN(2, 0), /* IPC_CLKIN */
4090 [ 9] = RCAR_GP_PIN(2, 9), /* GP2_09 */
4114 { PINMUX_BIAS_REG("PUEN3", 0xe60588c0, "PUD3", 0xe60588e0) {
4115 [ 0] = RCAR_GP_PIN(3, 0), /* CAN_CLK */
4124 [ 9] = RCAR_GP_PIN(3, 9), /* CANFD4_TX */
4148 { PINMUX_BIAS_REG("PUEN4", 0xe60600c0, "PUD4", 0xe60600e0) {
4149 [ 0] = RCAR_GP_PIN(4, 0), /* AVB0_RX_CTL */
4158 [ 9] = RCAR_GP_PIN(4, 9), /* AVB0_TD1 */
4182 { PINMUX_BIAS_REG("PUEN5", 0xe60608c0, "PUD5", 0xe60608e0) {
4183 [ 0] = RCAR_GP_PIN(5, 0), /* AVB1_RX_CTL */
4192 [ 9] = RCAR_GP_PIN(5, 9), /* AVB1_TD1 */
4216 { PINMUX_BIAS_REG("PUEN6", 0xe60680c0, "PUD6", 0xe60680e0) {
4217 [ 0] = RCAR_GP_PIN(6, 0), /* AVB2_RX_CTL */
4226 [ 9] = RCAR_GP_PIN(6, 9), /* AVB2_TD1 */
4250 { PINMUX_BIAS_REG("PUEN7", 0xe60688c0, "PUD7", 0xe60688e0) {
4251 [ 0] = RCAR_GP_PIN(7, 0), /* AVB3_RX_CTL */
4260 [ 9] = RCAR_GP_PIN(7, 9), /* AVB3_TD1 */
4284 { PINMUX_BIAS_REG("PUEN8", 0xe60690c0, "PUD8", 0xe60690e0) {
4285 [ 0] = RCAR_GP_PIN(8, 0), /* AVB4_RX_CTL */
4294 [ 9] = RCAR_GP_PIN(8, 9), /* AVB4_TD1 */
4318 { PINMUX_BIAS_REG("PUEN9", 0xe60698c0, "PUD9", 0xe60698e0) {
4319 [ 0] = RCAR_GP_PIN(9, 0), /* AVB5_RX_CTL */
4320 [ 1] = RCAR_GP_PIN(9, 1), /* AVB5_RXC */
4321 [ 2] = RCAR_GP_PIN(9, 2), /* AVB5_RD0 */
4322 [ 3] = RCAR_GP_PIN(9, 3), /* AVB5_RD1 */
4323 [ 4] = RCAR_GP_PIN(9, 4), /* AVB5_RD2 */
4324 [ 5] = RCAR_GP_PIN(9, 5), /* AVB5_RD3 */
4325 [ 6] = RCAR_GP_PIN(9, 6), /* AVB5_TX_CTL */
4326 [ 7] = RCAR_GP_PIN(9, 7), /* AVB5_TXC */
4327 [ 8] = RCAR_GP_PIN(9, 8), /* AVB5_TD0 */
4328 [ 9] = RCAR_GP_PIN(9, 9), /* AVB5_TD1 */
4329 [10] = RCAR_GP_PIN(9, 10), /* AVB5_TD2 */
4330 [11] = RCAR_GP_PIN(9, 11), /* AVB5_TD3 */
4331 [12] = RCAR_GP_PIN(9, 12), /* AVB5_TXCREFCLK */
4332 [13] = RCAR_GP_PIN(9, 13), /* AVB5_MDIO */
4333 [14] = RCAR_GP_PIN(9, 14), /* AVB5_MDC */
4334 [15] = RCAR_GP_PIN(9, 15), /* AVB5_MAGIC */
4335 [16] = RCAR_GP_PIN(9, 16), /* AVB5_PHY_INT */
4336 [17] = RCAR_GP_PIN(9, 17), /* AVB5_LINK */
4337 [18] = RCAR_GP_PIN(9, 18), /* AVB5_AVTP_MATCH */
4338 [19] = RCAR_GP_PIN(9, 19), /* AVB5_AVTP_CAPTURE */
4339 [20] = RCAR_GP_PIN(9, 20), /* AVB5_AVTP_PPS */
4364 .unlock_reg = 0x1ff, /* PMMRn mask */