Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:f_
1 // SPDX-License-Identifier: GPL-2.0
3 * R8A77970 processor support - PFC hardware block.
8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
10 * R-Car Gen3 processor support - PFC hardware block.
22 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
41 * F_() : just information
46 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
47 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
48 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
49 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
50 #define GPSR0_17 F_(DU_DB7, IP2_7_4)
51 #define GPSR0_16 F_(DU_DB6, IP2_3_0)
52 #define GPSR0_15 F_(DU_DB5, IP1_31_28)
53 #define GPSR0_14 F_(DU_DB4, IP1_27_24)
54 #define GPSR0_13 F_(DU_DB3, IP1_23_20)
55 #define GPSR0_12 F_(DU_DB2, IP1_19_16)
56 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
57 #define GPSR0_10 F_(DU_DG6, IP1_11_8)
58 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
59 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
60 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
61 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
62 #define GPSR0_5 F_(DU_DR7, IP0_23_20)
63 #define GPSR0_4 F_(DU_DR6, IP0_19_16)
64 #define GPSR0_3 F_(DU_DR5, IP0_15_12)
65 #define GPSR0_2 F_(DU_DR4, IP0_11_8)
66 #define GPSR0_1 F_(DU_DR3, IP0_7_4)
67 #define GPSR0_0 F_(DU_DR2, IP0_3_0)
70 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24)
71 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20)
72 #define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16)
73 #define GPSR1_24 F_(CANFD1_RX, IP8_15_12)
74 #define GPSR1_23 F_(CANFD1_TX, IP8_11_8)
75 #define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4)
76 #define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0)
77 #define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28)
97 #define GPSR1_0 F_(IRQ0, IP2_27_24)
100 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
101 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
102 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
103 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
104 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
105 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
106 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
107 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
108 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
109 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
110 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
111 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
112 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
113 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
114 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
115 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
116 #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
119 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
120 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
121 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
122 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
123 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
124 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
125 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
126 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
127 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
128 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
129 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
130 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
131 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
132 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
133 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
134 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
135 #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
138 #define GPSR4_5 F_(SDA2, IP7_27_24)
139 #define GPSR4_4 F_(SCL2, IP7_23_20)
140 #define GPSR4_3 F_(SDA1, IP7_19_16)
141 #define GPSR4_2 F_(SCL1, IP7_15_12)
142 #define GPSR4_1 F_(SDA0, IP7_11_8)
143 #define GPSR4_0 F_(SCL0, IP7_7_4)
163 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
164 … FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
165 … FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
166 … FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
167 …) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
168 …(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
169 …(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
170 …(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
171 …MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
172 …4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
173 …5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
174 …6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
175 …U_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
176 …U_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
177 …3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
178 …4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
179 …5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
180 …6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
181 …U_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
182 …(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
183 …C) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
184 …(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
185 …MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
186 …(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
187 …F2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
188 …) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
189 …2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
190 …SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
191 …_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
192 …_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
193 …P_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
194 …SCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
195 …TS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
196 …TS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
197 …HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
198 …HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
199 …) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
200 … FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
201 … FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
202 …) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
203 … FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
204 …MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
205 …(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
206 …(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
207 …MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
208 …(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
209 …MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
210 …ANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
211 …ANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
212 …ANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
213 …ATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
214 …ATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
215 …ATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
216 …TA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
217 …A9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
218 …A10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
219 …L4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
220 …A4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
221 …TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
222 …(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
223 …D_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
224 …_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
225 …WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
226 …WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
227 …RE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
228 …M(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
229 … FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
230 …2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
231 …3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
232 …(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
233 …GRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
234 …RF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
295 /* MOD_SEL0 */ /* 0 */ /* 1 */
325 PINMUX_RESERVED = 0,
331 #define F_(x, y) macro
339 #undef F_
342 #define F_(x, y) macro
349 #undef F_
732 * Pins not associated with a GPIO port.
744 /* - AVB0 ------------------------------------------------------------------- */
779 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
820 /* - CANFD Clock ------------------------------------------------------------ */
836 /* - CANFD0 ----------------------------------------------------------------- */
852 /* - CANFD1 ----------------------------------------------------------------- */
861 /* - DU --------------------------------------------------------------------- */
864 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
865 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
866 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
867 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
868 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
869 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
881 RCAR_GP_PIN(0, 18),
888 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
895 RCAR_GP_PIN(0, 21),
915 /* - HSCIF0 ----------------------------------------------------------------- */
918 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
925 RCAR_GP_PIN(0, 0),
932 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
938 /* - HSCIF1 ----------------------------------------------------------------- */
955 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
961 /* - HSCIF2 ----------------------------------------------------------------- */
984 /* - HSCIF3 ----------------------------------------------------------------- */
994 RCAR_GP_PIN(2, 0),
1007 /* - I2C0 ------------------------------------------------------------------- */
1010 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1016 /* - I2C1 ------------------------------------------------------------------- */
1025 /* - I2C2 ------------------------------------------------------------------- */
1034 /* - I2C3 ------------------------------------------------------------------- */
1050 /* - I2C4 ------------------------------------------------------------------- */
1059 /* - INTC-EX ---------------------------------------------------------------- */
1062 RCAR_GP_PIN(1, 0),
1069 RCAR_GP_PIN(0, 11),
1076 RCAR_GP_PIN(0, 12),
1083 RCAR_GP_PIN(0, 19),
1103 /* - MMC -------------------------------------------------------------------- */
1105 /* D[0:7] */
1107 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1125 /* - MSIOF0 ----------------------------------------------------------------- */
1163 RCAR_GP_PIN(4, 0),
1169 /* - MSIOF1 ----------------------------------------------------------------- */
1207 RCAR_GP_PIN(3, 0),
1213 /* - MSIOF2 ----------------------------------------------------------------- */
1216 RCAR_GP_PIN(2, 0),
1257 /* - MSIOF3 ----------------------------------------------------------------- */
1260 RCAR_GP_PIN(0, 20),
1267 RCAR_GP_PIN(0, 21),
1274 RCAR_GP_PIN(0, 6),
1281 RCAR_GP_PIN(0, 7),
1288 RCAR_GP_PIN(0, 5),
1295 RCAR_GP_PIN(0, 4),
1301 /* - PWM0 ------------------------------------------------------------------- */
1315 /* - PWM1 ------------------------------------------------------------------- */
1329 /* - PWM2 ------------------------------------------------------------------- */
1343 /* - PWM3 ------------------------------------------------------------------- */
1357 /* - PWM4 ------------------------------------------------------------------- */
1371 /* - QSPI0 ------------------------------------------------------------------ */
1374 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1380 /* - QSPI1 ------------------------------------------------------------------ */
1389 /* - RPC -------------------------------------------------------------------- */
1391 /* Octal-SPI flash: C/SCLK */
1393 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
1399 /* Octal-SPI flash: S#/CS, DQS */
1407 /* DQ[0:7] */
1411 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1441 /* - SCIF Clock ------------------------------------------------------------- */
1444 RCAR_GP_PIN(0, 18),
1457 /* - SCIF0 ------------------------------------------------------------------ */
1480 /* - SCIF1 ------------------------------------------------------------------ */
1483 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1510 /* - SCIF3 ------------------------------------------------------------------ */
1520 RCAR_GP_PIN(2, 0),
1533 /* - SCIF4 ------------------------------------------------------------------ */
1543 RCAR_GP_PIN(3, 9),
1556 /* - TMU -------------------------------------------------------------------- */
1586 /* - VIN0 ------------------------------------------------------------------- */
1590 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1626 RCAR_GP_PIN(2, 0),
1632 /* - VIN1 ------------------------------------------------------------------- */
1636 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1671 RCAR_GP_PIN(3, 0),
1762 SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
1763 SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
2085 #define F_(x, y) FN_##y macro
2087 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2088 GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2115 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2116 0, 0,
2117 0, 0,
2118 0, 0,
2119 0, 0,
2149 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
2150 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2172 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2173 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2195 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
2196 GROUP(-26, 1, 1, 1, 1, 1, 1),
2206 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2207 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2227 #undef F_
2230 #define F_(x, y) x, macro
2232 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2242 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2252 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2262 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2272 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2282 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2292 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2302 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2312 { PINMUX_CFG_REG_VAR("IPSR8", 0xe6060220, 32,
2313 GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
2324 #undef F_
2327 #define F_(x, y) x, macro
2329 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2330 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2332 /* RESERVED 31-12 */
2357 [POCCTRL0] = { 0xe6060380 },
2358 [POCCTRL1] = { 0xe6060384 },
2359 [POCCTRL2] = { 0xe6060388 },
2360 [TDSELCTRL] = { 0xe60603c0, },
2366 int bit = pin & 0x1f; in r8a77970_pin_to_pocctrl()
2369 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21): in r8a77970_pin_to_pocctrl()
2373 case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9): in r8a77970_pin_to_pocctrl()
2379 return bit - 10; in r8a77970_pin_to_pocctrl()
2381 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16): in r8a77970_pin_to_pocctrl()
2387 return 0; in r8a77970_pin_to_pocctrl()
2390 return -EINVAL; in r8a77970_pin_to_pocctrl()
2395 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2396 [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
2397 [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
2398 [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
2399 [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
2400 [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
2401 [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
2402 [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
2403 [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
2404 [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
2405 [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
2406 [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
2407 [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
2408 [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
2409 [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
2410 [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
2411 [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
2412 [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
2413 [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
2414 [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
2415 [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
2416 [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
2417 [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
2422 [26] = RCAR_GP_PIN(1, 0), /* IRQ0 */
2427 [31] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
2429 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2430 [ 0] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
2438 [ 8] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
2439 [ 9] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */
2446 [16] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
2455 [25] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
2463 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2464 [ 0] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
2465 [ 1] = RCAR_GP_PIN(4, 0), /* SCL0 */
2473 [ 9] = RCAR_GP_PIN(1, 3), /* AVB0_RD0 */
2479 [15] = RCAR_GP_PIN(1, 9), /* AVB0_TD0 */
2497 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2498 [ 0] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
2507 [ 9] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
2543 .unlock_reg = 0xe6060000, /* PMMR */