Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:f_
1 // SPDX-License-Identifier: GPL-2.0
3 * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
5 * Copyright (C) 2016-2019 Renesas Electronics Corp.
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
9 * R-Car Gen3 processor support - PFC hardware block.
22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
81 * F_() : just information
86 #define GPSR0_15 F_(D15, IP7_11_8)
87 #define GPSR0_14 F_(D14, IP7_7_4)
88 #define GPSR0_13 F_(D13, IP7_3_0)
89 #define GPSR0_12 F_(D12, IP6_31_28)
90 #define GPSR0_11 F_(D11, IP6_27_24)
91 #define GPSR0_10 F_(D10, IP6_23_20)
92 #define GPSR0_9 F_(D9, IP6_19_16)
93 #define GPSR0_8 F_(D8, IP6_15_12)
94 #define GPSR0_7 F_(D7, IP6_11_8)
95 #define GPSR0_6 F_(D6, IP6_7_4)
96 #define GPSR0_5 F_(D5, IP6_3_0)
97 #define GPSR0_4 F_(D4, IP5_31_28)
98 #define GPSR0_3 F_(D3, IP5_27_24)
99 #define GPSR0_2 F_(D2, IP5_23_20)
100 #define GPSR0_1 F_(D1, IP5_19_16)
101 #define GPSR0_0 F_(D0, IP5_15_12)
105 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
106 #define GPSR1_26 F_(WE1_N, IP5_7_4)
107 #define GPSR1_25 F_(WE0_N, IP5_3_0)
108 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
109 #define GPSR1_23 F_(RD_N, IP4_27_24)
110 #define GPSR1_22 F_(BS_N, IP4_23_20)
111 #define GPSR1_21 F_(CS1_N, IP4_19_16)
112 #define GPSR1_20 F_(CS0_N, IP4_15_12)
113 #define GPSR1_19 F_(A19, IP4_11_8)
114 #define GPSR1_18 F_(A18, IP4_7_4)
115 #define GPSR1_17 F_(A17, IP4_3_0)
116 #define GPSR1_16 F_(A16, IP3_31_28)
117 #define GPSR1_15 F_(A15, IP3_27_24)
118 #define GPSR1_14 F_(A14, IP3_23_20)
119 #define GPSR1_13 F_(A13, IP3_19_16)
120 #define GPSR1_12 F_(A12, IP3_15_12)
121 #define GPSR1_11 F_(A11, IP3_11_8)
122 #define GPSR1_10 F_(A10, IP3_7_4)
123 #define GPSR1_9 F_(A9, IP3_3_0)
124 #define GPSR1_8 F_(A8, IP2_31_28)
125 #define GPSR1_7 F_(A7, IP2_27_24)
126 #define GPSR1_6 F_(A6, IP2_23_20)
127 #define GPSR1_5 F_(A5, IP2_19_16)
128 #define GPSR1_4 F_(A4, IP2_15_12)
129 #define GPSR1_3 F_(A3, IP2_11_8)
130 #define GPSR1_2 F_(A2, IP2_7_4)
131 #define GPSR1_1 F_(A1, IP2_3_0)
132 #define GPSR1_0 F_(A0, IP1_31_28)
135 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
136 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
137 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
138 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
139 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
140 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
141 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
142 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
143 #define GPSR2_6 F_(PWM0, IP1_19_16)
144 #define GPSR2_5 F_(IRQ5, IP1_15_12)
145 #define GPSR2_4 F_(IRQ4, IP1_11_8)
146 #define GPSR2_3 F_(IRQ3, IP1_7_4)
147 #define GPSR2_2 F_(IRQ2, IP1_3_0)
148 #define GPSR2_1 F_(IRQ1, IP0_31_28)
149 #define GPSR2_0 F_(IRQ0, IP0_27_24)
152 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
153 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
154 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
155 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
156 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
157 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
158 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
159 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
160 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
161 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
162 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
163 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
164 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
165 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
166 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
167 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
170 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
171 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
172 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
173 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
174 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
175 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
176 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
177 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
178 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
179 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
180 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
181 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
182 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
183 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
184 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
185 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
186 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
187 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
190 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
191 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
192 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
194 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
196 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
197 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
199 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
200 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
201 #define GPSR5_14 F_(HTX0, IP13_19_16)
202 #define GPSR5_13 F_(HRX0, IP13_15_12)
203 #define GPSR5_12 F_(HSCK0, IP13_11_8)
204 #define GPSR5_11 F_(RX2_A, IP13_7_4)
205 #define GPSR5_10 F_(TX2_A, IP13_3_0)
206 #define GPSR5_9 F_(SCK2, IP12_31_28)
207 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
208 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
209 #define GPSR5_6 F_(TX1_A, IP12_19_16)
210 #define GPSR5_5 F_(RX1_A, IP12_15_12)
211 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
212 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
213 #define GPSR5_2 F_(TX0, IP12_3_0)
214 #define GPSR5_1 F_(RX0, IP11_31_28)
215 #define GPSR5_0 F_(SCK0, IP11_27_24)
218 #define GPSR6_31 F_(GP6_31, IP18_7_4)
219 #define GPSR6_30 F_(GP6_30, IP18_3_0)
220 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
221 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
222 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
223 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
224 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
225 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
226 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
227 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
228 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
229 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
230 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
231 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
232 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
233 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
234 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
235 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
239 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
240 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
241 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
242 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
243 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
244 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
245 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
246 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
247 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
248 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
249 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
258 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ …
259 …C) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
260 …) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
261 …) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
262 …) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
263 …) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
264 …) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
265 …F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F…
266 …F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) …
267 …F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0…
268 …F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4…
269 …F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) F…
270 …F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) F…
271 …TP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0…
272 … F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B)…
273 …_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(…
274 …OF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F…
275 …IOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F…
276 …IOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) …
277 …IOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) …
278 …F3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
279 …_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
280 …_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
281 …_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
282 …) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(…
283 …F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
284 …F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
285 …M(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_…
287 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ …
288 …IOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
289 …OF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
290 …OF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
291 …OF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
292 …CDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, …
293 …DOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
294 …OUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
295 …DOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
296 …N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
297 …) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) …
298 … FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F…
299 …F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CA…
300 …F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CAN…
301 …F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0…
302 …F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(C…
303 …QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
304 …OF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
305 …F3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
306 …F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
307 …F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
308 …SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
309 …YNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
310 …RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
311 …TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
312 …SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
313 …OF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
314 …4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
315 …4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
316 …(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ …
319 …(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
320 …RX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
321 …TX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
322 …F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0…
323 …F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(…
324 …F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F…
325 …F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0)…
326 …F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F…
327 …F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F…
328 … F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
329 …F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0,…
330 … FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
331 …NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
332 …M(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
333 … FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
334 …CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
335 …CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
336 …T0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
337 …T1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
338 …T2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
339 …T3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
340 …2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
341 …CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
342 …CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
343 …AT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
344 …AT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
345 …AT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
346 …AT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
347 …_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
348 …_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
349 …CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
350 …WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
351 …3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
352 …F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
354 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ …
355 …) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
356 … F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
357 …) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
358 …ST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) …
359 …B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) …
360 … F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0)…
361 …F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS…
362 …A_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0,…
363 …) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) …
364 …A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) …
365 …XD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0…
366 …XD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0…
367 …CK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0…
368 …F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_…
369 …F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO…
370 …F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF…
371 …F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C)…
372 …F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C)…
373 …F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F…
374 …) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) …
375 …F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(…
376 …FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0…
377 … FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0,…
378 …) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
379 …(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
380 …FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
381 …39) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
382 …9) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
384 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ …
385 …0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F…
386 …TA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
387 …_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
388 …F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0…
389 …IOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) …
390 …D_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(…
391 …_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_…
392 …A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F…
393 …_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F…
394 …6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
395 …S6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
396 …6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
397 …_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_…
398 …C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F…
399 …_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(T…
400 …_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F…
401 … FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_…
402 …LKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
403 …A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(…
404 …F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_…
405 …F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B…
406 …F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(…
407 …F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(R…
408 …F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_…
409 …F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IV…
410 …F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM…
411 …F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) …
495 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
496 …0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
498 …F1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
506 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
510 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
511 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
515 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
517 …) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
520 …0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
525 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
539 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
545 …4_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,…
588 * that can be set, such as drive-strength or pull-up/pull-down enable.
607 PINMUX_RESERVED = 0,
613 #define F_(x, y) macro
621 #undef F_
624 #define F_(x, y) macro
633 #undef F_
1548 * pin to the list without an associated function. The sh-pfc
1552 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1558 * Pins not associated with a GPIO port.
1570 /* - AUDIO CLOCK ------------------------------------------------------------ */
1572 /* CLK A */
1579 /* CLK A */
1586 /* CLK A */
1615 RCAR_GP_PIN(5, 0),
1692 /* - EtherAVB --------------------------------------------------------------- */
1716 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1778 /* - CAN ------------------------------------------------------------------ */
1788 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1801 /* - CAN Clock -------------------------------------------------------------- */
1810 /* - CAN FD --------------------------------------------------------------- */
1820 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1834 /* - DRIF0 --------------------------------------------------------------- */
1837 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1858 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1898 /* - DRIF1 --------------------------------------------------------------- */
1922 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1962 /* - DRIF2 --------------------------------------------------------------- */
1965 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2005 /* - DRIF3 --------------------------------------------------------------- */
2050 /* - DU --------------------------------------------------------------------- */
2053 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2054 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2069 /* R[7:0], G[7:0], B[7:0] */
2070 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2071 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2072 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2078 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2118 RCAR_GP_PIN(2, 0),
2131 /* - HSCIF0 ----------------------------------------------------------------- */
2153 /* - HSCIF1 ----------------------------------------------------------------- */
2185 RCAR_GP_PIN(5, 0),
2197 /* - HSCIF2 ----------------------------------------------------------------- */
2200 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2263 /* - HSCIF3 ----------------------------------------------------------------- */
2288 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2295 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2307 /* - HSCIF4 ----------------------------------------------------------------- */
2338 /* - I2C -------------------------------------------------------------------- */
2364 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2411 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2417 /* - INTC-EX ---------------------------------------------------------------- */
2420 RCAR_GP_PIN(2, 0),
2462 /* - MLB+ ------------------------------------------------------------------- */
2471 /* - MSIOF0 ----------------------------------------------------------------- */
2514 /* - MSIOF1 ----------------------------------------------------------------- */
2524 RCAR_GP_PIN(6, 9),
2559 RCAR_GP_PIN(5, 9),
2580 RCAR_GP_PIN(5, 0),
2685 RCAR_GP_PIN(3, 0),
2755 RCAR_GP_PIN(6, 0),
2797 RCAR_GP_PIN(3, 9),
2809 /* - MSIOF2 ----------------------------------------------------------------- */
2812 RCAR_GP_PIN(1, 9),
2854 RCAR_GP_PIN(0, 4),
2861 RCAR_GP_PIN(0, 5),
2868 RCAR_GP_PIN(0, 0),
2875 RCAR_GP_PIN(0, 1),
2882 RCAR_GP_PIN(0, 7),
2889 RCAR_GP_PIN(0, 6),
2917 RCAR_GP_PIN(2, 9),
2938 RCAR_GP_PIN(0, 8),
2945 RCAR_GP_PIN(0, 9),
2952 RCAR_GP_PIN(0, 12),
2959 RCAR_GP_PIN(0, 13),
2966 RCAR_GP_PIN(0, 11),
2973 RCAR_GP_PIN(0, 10),
2978 /* - MSIOF3 ----------------------------------------------------------------- */
2981 RCAR_GP_PIN(0, 0),
2988 RCAR_GP_PIN(0, 1),
2995 RCAR_GP_PIN(0, 14),
3002 RCAR_GP_PIN(0, 15),
3009 RCAR_GP_PIN(0, 3),
3016 RCAR_GP_PIN(0, 2),
3030 RCAR_GP_PIN(1, 0),
3150 RCAR_GP_PIN(2, 0),
3170 /* - PWM0 --------------------------------------------------------------------*/
3178 /* - PWM1 --------------------------------------------------------------------*/
3193 /* - PWM2 --------------------------------------------------------------------*/
3208 /* - PWM3 --------------------------------------------------------------------*/
3211 RCAR_GP_PIN(1, 0),
3223 /* - PWM4 --------------------------------------------------------------------*/
3238 /* - PWM5 --------------------------------------------------------------------*/
3253 /* - PWM6 --------------------------------------------------------------------*/
3269 /* - QSPI0 ------------------------------------------------------------------ */
3287 /* - QSPI1 ------------------------------------------------------------------ */
3306 /* - SCIF0 ------------------------------------------------------------------ */
3316 RCAR_GP_PIN(5, 0),
3328 /* - SCIF1 ------------------------------------------------------------------ */
3358 /* - SCIF2 ------------------------------------------------------------------ */
3368 RCAR_GP_PIN(5, 9),
3380 /* - SCIF3 ------------------------------------------------------------------ */
3409 /* - SCIF4 ------------------------------------------------------------------ */
3447 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3454 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3461 RCAR_GP_PIN(0, 8),
3468 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3473 /* - SCIF5 ------------------------------------------------------------------ */
3498 RCAR_GP_PIN(5, 0),
3504 /* - SCIF Clock ------------------------------------------------------------- */
3514 RCAR_GP_PIN(5, 9),
3520 /* - SDHI0 ------------------------------------------------------------------ */
3522 /* D[0:3] */
3532 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3551 /* - SDHI1 ------------------------------------------------------------------ */
3553 /* D[0:3] */
3554 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3582 /* - SDHI2 ------------------------------------------------------------------ */
3584 /* D[0:7] */
3587 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3598 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3638 /* - SDHI3 ------------------------------------------------------------------ */
3640 /* D[0:7] */
3641 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3681 /* - SSI -------------------------------------------------------------------- */
3691 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3775 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3858 /* - TMU -------------------------------------------------------------------- */
3888 /* - TPU ------------------------------------------------------------------- */
3918 /* - USB0 ------------------------------------------------------------------- */
3926 /* - USB1 ------------------------------------------------------------------- */
3935 /* - USB30 ------------------------------------------------------------------ */
3944 /* - VIN4 ------------------------------------------------------------------- */
3946 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3947 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3948 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3952 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3953 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3954 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3974 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3975 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3976 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3990 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3991 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3992 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3993 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3994 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3998 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3999 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4000 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4001 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4018 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4022 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4026 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4027 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4028 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4029 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4074 /* - VIN5 ------------------------------------------------------------------- */
4076 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4077 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4078 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4079 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4097 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
5095 #define F_(x, y) FN_##y macro
5097 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5098 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5119 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5120 0, 0,
5121 0, 0,
5122 0, 0,
5153 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5154 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5174 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5175 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5196 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5197 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5220 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5221 0, 0,
5222 0, 0,
5223 0, 0,
5224 0, 0,
5225 0, 0,
5226 0, 0,
5254 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5288 { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5289 GROUP(-28, 1, 1, 1, 1),
5297 #undef F_
5300 #define F_(x, y) x, macro
5302 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5312 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5322 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5332 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5342 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5352 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5362 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5372 { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5373 GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5384 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5394 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5404 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5414 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5424 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5434 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5444 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5454 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5464 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5474 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5484 { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5485 GROUP(-24, 4, 4),
5491 #undef F_
5494 #define F_(x, y) x, macro
5496 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5497 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5498 1, 1, 1, 2, 2, 1, 2, -3),
5519 /* RESERVED 2, 1, 0 */ ))
5521 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5523 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
5549 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5551 -16, 1),
5565 /* RESERVED 16-1 */
5572 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5580 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
5582 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5590 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
5592 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5600 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
5602 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5608 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5610 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5612 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5616 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5620 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5622 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5627 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5630 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5632 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5638 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5640 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5642 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5650 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5652 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5660 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5662 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5665 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5666 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5667 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5668 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5669 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5670 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5672 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5673 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5674 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5675 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5676 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5677 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5678 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5679 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5680 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5682 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5683 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5684 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5685 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5690 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
5692 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5697 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5700 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5705 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5707 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5711 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5714 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5715 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5717 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5725 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5727 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5735 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5737 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5742 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5745 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5747 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5753 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5755 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5757 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5765 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5767 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5775 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5777 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5785 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5787 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5788 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5795 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5797 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5805 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5807 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5825 [POCCTRL] = { 0xe6060380, },
5826 [TDSELCTRL] = { 0xe60603c0, },
5832 int bit = -EINVAL; in r8a7796_pin_to_pocctrl()
5836 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) in r8a7796_pin_to_pocctrl()
5837 bit = pin & 0x1f; in r8a7796_pin_to_pocctrl()
5839 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) in r8a7796_pin_to_pocctrl()
5840 bit = (pin & 0x1f) + 12; in r8a7796_pin_to_pocctrl()
5846 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5847 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5856 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5876 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5880 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5881 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5884 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5890 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5893 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5902 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5914 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5915 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5924 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
5925 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5926 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5927 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5928 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5929 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5930 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5931 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5932 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5933 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5934 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5935 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5936 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5937 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5938 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5939 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5940 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5941 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5948 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5949 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
5958 [ 9] = PIN_ASEBRK, /* ASEBRK */
5959 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5968 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5971 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5980 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5982 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5983 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5992 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5995 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6004 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6016 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6017 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6024 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6026 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6033 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6050 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6051 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6060 [ 9] = SH_PFC_PIN_NONE,
6097 .unlock_reg = 0xe6060000, /* PMMR */
6122 .unlock_reg = 0xe6060000, /* PMMR */
6149 .unlock_reg = 0xe6060000, /* PMMR */