Lines Matching +full:0 +full:xe6060000
18 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
45 PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
80 PINMUX_RESERVED = 0,
1527 RCAR_GP_PIN(5, 0),
1627 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1651 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1764 RCAR_GP_PIN(1, 0),
1773 RCAR_GP_PIN(5, 0),
1799 /* R[7:0], G[7:0], B[7:0] */
1802 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
1885 /* R[7:0], G[7:0], B[7:0] */
1888 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1976 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2007 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2040 RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
2047 RCAR_GP_PIN(1, 0),
2091 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2098 RCAR_GP_PIN(0, 10),
2105 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2134 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2149 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2156 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2170 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2206 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2228 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2300 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2343 RCAR_GP_PIN(0, 7),
2350 RCAR_GP_PIN(0, 0),
2364 RCAR_GP_PIN(0, 10),
2378 RCAR_GP_PIN(5, 0),
2392 /* D[0:7] */
2455 RCAR_GP_PIN(0, 26),
2462 RCAR_GP_PIN(0, 27),
2469 RCAR_GP_PIN(0, 28),
2476 RCAR_GP_PIN(0, 29),
2483 RCAR_GP_PIN(0, 24),
2490 RCAR_GP_PIN(0, 25),
2540 RCAR_GP_PIN(1, 0),
2568 RCAR_GP_PIN(0, 30),
2575 RCAR_GP_PIN(0, 31),
2666 RCAR_GP_PIN(0, 13),
2678 RCAR_GP_PIN(0, 16),
2690 RCAR_GP_PIN(0, 21),
2702 RCAR_GP_PIN(4, 0),
2708 RCAR_GP_PIN(0, 10),
2720 RCAR_GP_PIN(0, 7),
2801 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2808 RCAR_GP_PIN(0, 10),
2888 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2895 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2931 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2938 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2960 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2982 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2989 RCAR_GP_PIN(0, 13),
3039 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
3068 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
3075 RCAR_GP_PIN(0, 0),
3090 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
3119 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
3141 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
3148 RCAR_GP_PIN(0, 19),
3155 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
3163 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
3170 RCAR_GP_PIN(0, 16),
3214 /* D[0:3] */
3223 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3244 /* D[0:3] */
3274 /* D[0:3] */
3473 RCAR_GP_PIN(5, 0),
3567 RCAR_GP_PIN(4, 0),
3585 RCAR_GP_PIN(1, 0),
3591 RCAR_GP_PIN(0, 22),
3609 RCAR_GP_PIN(0, 21),
3716 RCAR_GP_PIN(3, 0),
4630 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4664 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
4665 0, 0,
4666 0, 0,
4667 0, 0,
4668 0, 0,
4669 0, 0,
4670 0, 0,
4698 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
4732 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
4766 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
4800 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
4801 0, 0,
4802 0, 0,
4803 0, 0,
4804 0, 0,
4834 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
4835 0, 0,
4836 0, 0,
4837 0, 0,
4838 0, 0,
4839 0, 0,
4840 0, 0,
4868 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4873 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
4875 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
4877 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
4883 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
4905 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
4910 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4926 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
4928 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
4930 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
4932 FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
4933 0, 0, 0,
4940 0, 0, 0,
4942 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
4944 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
4948 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, ))
4950 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4954 FN_A20, FN_SPCLK, 0, 0,
4957 0, 0, 0, 0,
4960 0, 0, 0, 0,
4963 0, 0, 0, 0,
4966 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
4972 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
4974 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
4976 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
4978 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
4980 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
4982 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
4984 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, ))
4986 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4996 0, 0, 0,
4999 0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
5002 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
5005 0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
5008 0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
5018 FN_A25, FN_SSL, FN_ATARD1_N, 0,
5020 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
5022 FN_A23, FN_IO2, 0, FN_ATAWR1_N,
5024 FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
5026 FN_A21, FN_MOSI_IO0, 0, 0, ))
5028 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5032 FN_DU0_DG4, FN_LCDOUT12, 0, 0,
5034 FN_DU0_DG3, FN_LCDOUT11, 0, 0,
5036 FN_DU0_DG2, FN_LCDOUT10, 0, 0,
5039 0, 0, 0, 0,
5042 0, 0, 0, 0,
5044 FN_DU0_DR7, FN_LCDOUT23, 0, 0,
5046 FN_DU0_DR6, FN_LCDOUT22, 0, 0,
5048 FN_DU0_DR5, FN_LCDOUT21, 0, 0,
5050 FN_DU0_DR4, FN_LCDOUT20, 0, 0,
5052 FN_DU0_DR3, FN_LCDOUT19, 0, 0,
5054 FN_DU0_DR2, FN_LCDOUT18, 0, 0,
5057 0, 0, 0, 0,
5060 0, 0, 0, 0,
5062 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, ))
5064 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5069 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
5071 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
5073 FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
5075 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
5077 FN_DU0_DB7, FN_LCDOUT7, 0, 0,
5079 FN_DU0_DB6, FN_LCDOUT6, 0, 0,
5081 FN_DU0_DB5, FN_LCDOUT5, 0, 0,
5083 FN_DU0_DB4, FN_LCDOUT4, 0, 0,
5085 FN_DU0_DB3, FN_LCDOUT3, 0, 0,
5087 FN_DU0_DB2, FN_LCDOUT2, 0, 0,
5090 FN_CAN0_TX_C, 0, 0, 0,
5093 FN_CAN0_RX_C, 0, 0, 0,
5095 FN_DU0_DG7, FN_LCDOUT15, 0, 0,
5097 FN_DU0_DG6, FN_LCDOUT14, 0, 0,
5099 FN_DU0_DG5, FN_LCDOUT13, 0, 0, ))
5101 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5107 FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
5110 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
5113 FN_AVB_COL, 0, 0, 0,
5116 FN_AVB_RX_ER, 0, 0, 0,
5119 FN_AVB_RXD7, 0, 0, 0,
5139 FN_DU0_CDE, FN_QPOLB, 0, 0,
5141 FN_DU0_DISP, FN_QPOLA, 0, 0,
5143 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
5144 0,
5146 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
5148 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5156 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
5159 FN_SSI_SCK6_B, 0, 0, 0,
5162 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
5165 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
5168 FN_SSI_SCK5_B, 0, 0, 0,
5171 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
5174 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
5177 FN_AVB_TXD2, FN_ADICHS0, 0, 0,
5180 FN_AVB_TXD1, FN_ADICLK, 0, 0,
5183 FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, ))
5185 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5190 0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
5193 0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
5196 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
5199 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
5202 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
5207 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
5210 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
5213 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
5216 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
5219 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
5221 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5227 FN_SSI_SDATA1_B, 0, 0, 0,
5230 FN_SSI_WS1_B, 0, 0, 0,
5233 FN_SSI_SCK1_B, 0, 0, 0,
5236 FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
5243 0, FN_FMIN_B, 0, 0,
5246 0, FN_FMCLK_B, 0, 0,
5249 0, FN_BPFCLK_B, 0, 0,
5252 0, FN_TPUTO1_C, 0, 0,
5255 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, ))
5257 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5261 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
5264 0, 0, 0, 0,
5267 FN_SSI_SDATA4_B, 0, 0, 0,
5270 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
5273 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
5276 FN_SSI_SDATA9_B, 0, 0, 0,
5279 0, 0, 0, 0,
5282 0, 0, 0, 0,
5285 0, 0, 0, 0,
5288 0, 0, 0, 0,
5291 0, 0, 0, 0, ))
5293 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5299 0, 0, 0, 0,
5302 0, 0, 0, 0,
5305 0, 0, 0, 0,
5308 FN_CAN_CLK_D, 0, 0, 0,
5315 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
5318 FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
5320 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
5323 0, 0, 0, 0,
5326 0, 0, 0, 0, ))
5328 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5333 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
5334 FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
5336 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
5337 FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
5340 FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
5343 FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
5346 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
5348 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
5350 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
5352 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
5355 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
5358 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
5361 0, FN_DREQ1_N_B, 0, 0, ))
5363 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5369 FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
5372 FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
5375 FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
5378 FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
5381 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
5384 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
5387 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
5390 FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
5393 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
5395 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5406 FN_SEL_DARC_4, 0, 0, 0,
5413 FN_SEL_I2C00_4, 0, 0, 0,
5416 FN_SEL_I2C01_4, 0, 0, 0,
5419 FN_SEL_I2C02_4, 0, 0, 0,
5422 FN_SEL_I2C03_4, 0, 0, 0,
5425 FN_SEL_I2C04_4, 0, 0, 0,
5430 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5435 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5454 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
5480 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5487 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
5489 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
5494 FN_SEL_SCIF4_4, 0, 0, 0,
5520 if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) in r8a7794_pin_to_pocctrl()
5523 *pocctrl = 0xe606006c; in r8a7794_pin_to_pocctrl()
5525 switch (pin & 0x1f) { in r8a7794_pin_to_pocctrl()
5530 case 0 ... 5: in r8a7794_pin_to_pocctrl()
5532 return 22 - (pin & 0x1f); in r8a7794_pin_to_pocctrl()
5534 return 47 - (pin & 0x1f); in r8a7794_pin_to_pocctrl()
5541 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
5542 [ 0] = RCAR_GP_PIN(0, 0), /* D0 */
5543 [ 1] = RCAR_GP_PIN(0, 1), /* D1 */
5544 [ 2] = RCAR_GP_PIN(0, 2), /* D2 */
5545 [ 3] = RCAR_GP_PIN(0, 3), /* D3 */
5546 [ 4] = RCAR_GP_PIN(0, 4), /* D4 */
5547 [ 5] = RCAR_GP_PIN(0, 5), /* D5 */
5548 [ 6] = RCAR_GP_PIN(0, 6), /* D6 */
5549 [ 7] = RCAR_GP_PIN(0, 7), /* D7 */
5550 [ 8] = RCAR_GP_PIN(0, 8), /* D8 */
5551 [ 9] = RCAR_GP_PIN(0, 9), /* D9 */
5552 [10] = RCAR_GP_PIN(0, 10), /* D10 */
5553 [11] = RCAR_GP_PIN(0, 11), /* D11 */
5554 [12] = RCAR_GP_PIN(0, 12), /* D12 */
5555 [13] = RCAR_GP_PIN(0, 13), /* D13 */
5556 [14] = RCAR_GP_PIN(0, 14), /* D14 */
5557 [15] = RCAR_GP_PIN(0, 15), /* D15 */
5558 [16] = RCAR_GP_PIN(0, 16), /* A0 */
5559 [17] = RCAR_GP_PIN(0, 17), /* A1 */
5560 [18] = RCAR_GP_PIN(0, 18), /* A2 */
5561 [19] = RCAR_GP_PIN(0, 19), /* A3 */
5562 [20] = RCAR_GP_PIN(0, 20), /* A4 */
5563 [21] = RCAR_GP_PIN(0, 21), /* A5 */
5564 [22] = RCAR_GP_PIN(0, 22), /* A6 */
5565 [23] = RCAR_GP_PIN(0, 23), /* A7 */
5566 [24] = RCAR_GP_PIN(0, 24), /* A8 */
5567 [25] = RCAR_GP_PIN(0, 25), /* A9 */
5568 [26] = RCAR_GP_PIN(0, 26), /* A10 */
5569 [27] = RCAR_GP_PIN(0, 27), /* A11 */
5570 [28] = RCAR_GP_PIN(0, 28), /* A12 */
5571 [29] = RCAR_GP_PIN(0, 29), /* A13 */
5572 [30] = RCAR_GP_PIN(0, 30), /* A14 */
5573 [31] = RCAR_GP_PIN(0, 31), /* A15 */
5575 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
5577 [ 0] = RCAR_GP_PIN(1, 0), /* A16 */
5610 { PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) {
5612 [ 0] = SH_PFC_PIN_NONE,
5645 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
5646 [ 0] = RCAR_GP_PIN(2, 0), /* DU0_DR0 */
5679 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
5680 [ 0] = RCAR_GP_PIN(3, 2), /* VI0_DATA1_VI0_B1 */
5710 [30] = RCAR_GP_PIN(4, 0), /* I2C1_SCL */
5713 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
5714 [ 0] = RCAR_GP_PIN(4, 2), /* MSIOF0_RXD */
5744 [30] = RCAR_GP_PIN(5, 0), /* SSI_SDATA7 */
5747 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
5748 [ 0] = RCAR_GP_PIN(5, 2), /* SSI_WS0129 */
5770 [22] = RCAR_GP_PIN(3, 0), /* VI0_CLK */
5781 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
5782 [ 0] = RCAR_GP_PIN(6, 1), /* SD0_CMD */
5819 { .soc_id = "r8a7794", .revision = "ES1.0" },
5827 sh_pfc_write(pfc, 0xe6060068, 0x55555500); in r8a7794_pinmux_soc_init()
5829 return 0; in r8a7794_pinmux_soc_init()
5843 .unlock_reg = 0xe6060000, /* PMMR */
5866 .unlock_reg = 0xe6060000, /* PMMR */