Lines Matching +full:0 +full:xe6060000
14 PORT_GP_CFG_29(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
39 PINMUX_RESERVED = 0,
782 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
784 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(6, 11),
806 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
808 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
856 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
857 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
858 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
859 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
860 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
861 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
872 /* R[7:0], G[7:0], B[7:0] */
873 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
874 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
875 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
876 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
877 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
878 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
879 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
880 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
881 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
896 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
903 RCAR_GP_PIN(0, 26),
910 RCAR_GP_PIN(0, 27),
917 RCAR_GP_PIN(0, 28),
925 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1056 RCAR_GP_PIN(10, 0),
1203 /* DAT[0-3] */
1314 RCAR_GP_PIN(4, 0),
1464 RCAR_GP_PIN(5, 0),
1510 RCAR_GP_PIN(6, 0),
1556 RCAR_GP_PIN(7, 0),
1598 RCAR_GP_PIN(8, 0),
1640 RCAR_GP_PIN(9, 0),
1968 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
1969 0, 0,
1970 0, 0,
1971 0, 0,
2002 { PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
2031 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
2065 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
2066 0, 0,
2067 0, 0,
2068 0, 0,
2069 0, 0,
2099 { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060014, 32,
2122 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060018, 32,
2145 { PINMUX_CFG_REG_VAR("GPSR6", 0xE606001C, 32,
2168 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6060020, 32,
2191 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6060024, 32,
2214 { PINMUX_CFG_REG_VAR("GPSR9", 0xE6060028, 32,
2237 { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
2271 { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
2272 0, 0,
2273 0, 0,
2305 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2313 FN_DU0_DB7_C5, 0,
2315 FN_DU0_DB6_C4, 0,
2317 FN_DU0_DB5_C3, 0,
2319 FN_DU0_DB4_C2, 0,
2321 FN_DU0_DB3_C1, 0,
2323 FN_DU0_DB2_C0, 0,
2325 FN_DU0_DB1, 0,
2327 FN_DU0_DB0, 0,
2329 FN_DU0_DG7_Y3_DATA15, 0,
2331 FN_DU0_DG6_Y2_DATA14, 0,
2333 FN_DU0_DG5_Y1_DATA13, 0,
2335 FN_DU0_DG4_Y0_DATA12, 0,
2337 FN_DU0_DG3_C7_DATA11, 0,
2339 FN_DU0_DG2_C6_DATA10, 0,
2341 FN_DU0_DG1_DATA9, 0,
2343 FN_DU0_DG0_DATA8, 0,
2345 FN_DU0_DR7_Y9_DATA7, 0,
2347 FN_DU0_DR6_Y8_DATA6, 0,
2349 FN_DU0_DR5_Y7_DATA5, 0,
2351 FN_DU0_DR4_Y6_DATA4, 0,
2353 FN_DU0_DR3_Y5_DATA3, 0,
2355 FN_DU0_DR2_Y4_DATA2, 0,
2357 FN_DU0_DR1_DATA1, 0,
2359 FN_DU0_DR0_DATA0, 0 ))
2361 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2380 FN_DU1_DG7_Y3_DATA11, 0,
2382 FN_DU1_DG6_Y2_DATA10, 0,
2384 FN_DU1_DG5_Y1_DATA9, 0,
2386 FN_DU1_DG4_Y0_DATA8, 0,
2388 FN_DU1_DG3_C7_DATA7, 0,
2390 FN_DU1_DG2_C6_DATA6, 0,
2392 FN_DU1_DR7_DATA5, 0,
2394 FN_DU1_DR6_DATA4, 0,
2396 FN_DU1_DR5_Y7_DATA3, 0,
2398 FN_DU1_DR4_Y6_DATA2, 0,
2400 FN_DU1_DR3_Y5_DATA1, 0,
2402 FN_DU1_DR2_Y4_DATA0, 0,
2404 FN_DU0_CDE, 0,
2406 FN_DU0_DISP, 0,
2408 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
2410 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2412 FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
2414 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2455 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2491 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2505 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
2507 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
2509 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
2511 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
2513 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
2515 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
2517 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
2519 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
2523 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
2529 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2559 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2565 FN_DREQ1_N, FN_RX3, 0, 0,
2567 FN_TX3, 0,
2569 FN_DACK1, FN_SCK3, 0, 0,
2571 FN_DREQ0_N, FN_RX2, 0, 0,
2573 FN_DACK0, FN_TX2, 0, 0,
2575 FN_DRACK0, FN_SCK2, 0, 0,
2593 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2600 FN_AUDIO_CLKB, 0,
2602 FN_AUDIO_CLKA, 0,
2604 FN_AUDIO_CLKOUT, 0,
2606 FN_SSI_SDATA4, 0,
2608 FN_SSI_WS4, 0,
2610 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
2612 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
2614 FN_SSI_WS34, FN_TPU0TO1, 0, 0,
2616 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
2618 FN_PWM4, 0,
2620 FN_PWM3, 0,
2622 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
2624 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2626 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
2632 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
2633 [ 0] = RCAR_GP_PIN(0, 0), /* DU0_DR0_DATA0 */
2634 [ 1] = RCAR_GP_PIN(0, 1), /* DU0_DR1_DATA1 */
2635 [ 2] = RCAR_GP_PIN(0, 2), /* DU0_DR2_Y4_DATA2 */
2636 [ 3] = RCAR_GP_PIN(0, 3), /* DU0_DR3_Y5_DATA3 */
2637 [ 4] = RCAR_GP_PIN(0, 4), /* DU0_DR4_Y6_DATA4 */
2638 [ 5] = RCAR_GP_PIN(0, 5), /* DU0_DR5_Y7_DATA5 */
2639 [ 6] = RCAR_GP_PIN(0, 6), /* DU0_DR6_Y8_DATA6 */
2640 [ 7] = RCAR_GP_PIN(0, 7), /* DU0_DR7_Y9_DATA7 */
2641 [ 8] = RCAR_GP_PIN(0, 8), /* DU0_DG0_DATA8 */
2642 [ 9] = RCAR_GP_PIN(0, 9), /* DU0_DG1_DATA9 */
2643 [10] = RCAR_GP_PIN(0, 10), /* DU0_DG2_C6_DATA10 */
2644 [11] = RCAR_GP_PIN(0, 11), /* DU0_DG3_C7_DATA11 */
2645 [12] = RCAR_GP_PIN(0, 12), /* DU0_DG4_Y0_DATA12 */
2646 [13] = RCAR_GP_PIN(0, 13), /* DU0_DG5_Y1_DATA13 */
2647 [14] = RCAR_GP_PIN(0, 14), /* DU0_DG6_Y2_DATA14 */
2648 [15] = RCAR_GP_PIN(0, 15), /* DU0_DG7_Y3_DATA15 */
2649 [16] = RCAR_GP_PIN(0, 16), /* DU0_DB0 */
2650 [17] = RCAR_GP_PIN(0, 17), /* DU0_DB1 */
2651 [18] = RCAR_GP_PIN(0, 18), /* DU0_DB2_C0 */
2652 [19] = RCAR_GP_PIN(0, 19), /* DU0_DB3_C1 */
2653 [20] = RCAR_GP_PIN(0, 20), /* DU0_DB4_C2 */
2654 [21] = RCAR_GP_PIN(0, 21), /* DU0_DB5_C3 */
2655 [22] = RCAR_GP_PIN(0, 22), /* DU0_DB6_C4 */
2656 [23] = RCAR_GP_PIN(0, 23), /* DU0_DB7_C5 */
2657 [24] = RCAR_GP_PIN(0, 24), /* DU0_EXHSYNC/DU0_HSYNC */
2658 [25] = RCAR_GP_PIN(0, 25), /* DU0_EXVSYNC/DU0_VSYNC */
2659 [26] = RCAR_GP_PIN(0, 26), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */
2660 [27] = RCAR_GP_PIN(0, 27), /* DU0_DISP */
2661 [28] = RCAR_GP_PIN(0, 28), /* DU0_CDE */
2666 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
2667 [ 0] = RCAR_GP_PIN(1, 0), /* DU1_DR2_Y4_DATA0 */
2700 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
2701 [ 0] = RCAR_GP_PIN(2, 0), /* D0 */
2734 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
2735 [ 0] = RCAR_GP_PIN(3, 0), /* A16 */
2768 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
2769 [ 0] = RCAR_GP_PIN(4, 0), /* VI0_CLK */
2802 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
2803 [ 0] = RCAR_GP_PIN(5, 0), /* VI1_CLK */
2836 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
2837 [ 0] = RCAR_GP_PIN(6, 0), /* VI2_CLK */
2870 { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
2871 [ 0] = RCAR_GP_PIN(7, 0), /* VI3_CLK */
2904 { PINMUX_BIAS_REG("PUPR8", 0xe6060120, "N/A", 0) {
2905 [ 0] = RCAR_GP_PIN(8, 0), /* VI4_CLK */
2938 { PINMUX_BIAS_REG("PUPR9", 0xe6060124, "N/A", 0) {
2939 [ 0] = RCAR_GP_PIN(9, 0), /* VI5_CLK */
2972 { PINMUX_BIAS_REG("PUPR10", 0xe6060128, "N/A", 0) {
2973 [ 0] = RCAR_GP_PIN(10, 0), /* HSCK0 */
3006 { PINMUX_BIAS_REG("PUPR11", 0xe606012c, "N/A", 0) {
3007 [ 0] = RCAR_GP_PIN(11, 0), /* PWM0 */
3040 { PINMUX_BIAS_REG("PUPR12", 0xe6060130, "N/A", 0) {
3042 [ 0] = PIN_DU0_DOTCLKIN, /* DU0_DOTCLKIN */
3075 { PINMUX_BIAS_REG("N/A", 0, "PUPR12", 0xe6060130) {
3077 [ 0] = SH_PFC_PIN_NONE,
3121 .unlock_reg = 0xe6060000, /* PMMR */