Lines Matching +full:0 +full:xe6060000
15 * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
19 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
65 PINMUX_RESERVED = 0,
1746 /* ADICHS 0 */
1750 /* ADICHS 0 */
1778 /* ADICHS B 0 */
1782 /* ADICHS B 0 */
1878 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1901 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2072 /* R[7:0], G[7:0], B[7:0] */
2075 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2184 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2211 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2232 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2353 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2375 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2389 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2483 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2596 /* D[0:7] */
2607 /* D[0:7] */
2670 RCAR_GP_PIN(0, 16),
2677 RCAR_GP_PIN(0, 17),
2684 RCAR_GP_PIN(0, 18),
2691 RCAR_GP_PIN(0, 19),
2698 RCAR_GP_PIN(0, 21),
2705 RCAR_GP_PIN(0, 20),
2756 RCAR_GP_PIN(0, 22),
2763 RCAR_GP_PIN(0, 23),
2770 RCAR_GP_PIN(0, 24),
2777 RCAR_GP_PIN(0, 25),
2784 RCAR_GP_PIN(0, 27),
2791 RCAR_GP_PIN(0, 26),
2871 RCAR_GP_PIN(0, 28),
2878 RCAR_GP_PIN(0, 30),
2885 RCAR_GP_PIN(0, 29),
2892 RCAR_GP_PIN(0, 27),
2899 RCAR_GP_PIN(0, 26),
2979 RCAR_GP_PIN(3, 0),
3152 RCAR_GP_PIN(0, 16),
3212 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3235 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3386 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3423 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3452 RCAR_GP_PIN(1, 0),
3539 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3590 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3618 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3746 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3784 /* D[0:3] */
3793 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3814 /* D[0:3] */
3844 /* D[0:3] */
3894 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4254 RCAR_GP_PIN(4, 0),
4273 RCAR_GP_PIN(5, 0), /* HSYNC */
4300 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
5416 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
5450 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
5451 0, 0,
5452 0, 0,
5453 0, 0,
5454 0, 0,
5455 0, 0,
5456 0, 0,
5484 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
5518 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
5552 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
5586 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
5620 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
5654 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
5655 0, 0,
5656 0, 0,
5657 0, 0,
5658 0, 0,
5659 0, 0,
5660 0, 0,
5688 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5695 0, 0,
5698 0, 0,
5701 0, 0,
5704 0, 0,
5707 0, 0,
5710 0, 0,
5713 0, 0, 0,
5715 FN_D15, 0,
5717 FN_D14, 0,
5719 FN_D13, 0,
5721 FN_D12, 0,
5723 FN_D11, 0,
5725 FN_D10, 0,
5727 FN_D9, 0,
5729 FN_D8, 0,
5731 FN_D7, 0,
5733 FN_D6, 0,
5735 FN_D5, 0,
5737 FN_D4, 0,
5739 FN_D3, 0,
5741 FN_D2, 0,
5743 FN_D1, 0,
5745 FN_D0, 0, ))
5747 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5751 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5752 0, 0, 0,
5754 FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
5755 0, 0, 0, 0,
5757 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5758 0, 0, 0,
5761 0, 0, 0, 0, 0, 0,
5764 0, 0, 0,
5767 0, 0, 0, 0,
5770 0, 0, 0, 0,
5773 0, 0, 0, 0,
5775 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5777 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
5779 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
5782 0, 0, ))
5784 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5790 FN_ATAG0_N, 0, FN_EX_WAIT1,
5791 0, 0,
5793 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5795 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5797 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
5799 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
5802 0, 0,
5805 0, 0, 0,
5808 0, 0, 0,
5811 0, 0, 0,
5813 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5815 FN_A20, FN_SPCLK, 0, 0,
5817 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5818 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
5820 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5827 0, 0, 0,
5831 0, 0, 0,
5833 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5836 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5838 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5840 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5844 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5847 0, 0, 0,
5850 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5853 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5855 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5856 0, 0, 0, ))
5858 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5866 0, 0,
5868 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5870 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5872 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5874 FN_SSI_SDATA3, 0,
5876 FN_SSI_WS34, 0,
5878 FN_SSI_SCK34, 0,
5881 0, 0, 0, 0,
5885 0, 0,
5888 0, 0, 0,
5893 FN_GLO_I1_D, 0, 0, 0,
5897 0, 0, 0,
5902 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5907 0, 0, 0, 0, 0,
5910 0, 0, 0, 0,
5912 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5914 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5916 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5919 0, 0, 0, 0,
5921 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5924 0, 0, 0, 0,
5927 0, 0, 0, 0,
5931 0, 0,
5935 0, 0,
5939 0, 0, ))
5941 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5948 0, 0, 0,
5952 0, 0, 0,
5956 0, 0, 0,
5961 0, 0, 0, 0,
5963 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0,
5965 FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0,
5967 FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0,
5969 FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0,
5975 0, 0,
5979 0, 0, ))
5981 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5988 0, 0,
5992 0, 0,
5996 0, 0,
5998 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
6000 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
6002 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
6004 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
6006 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
6008 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
6012 0, 0,
6016 0, 0,
6020 0, 0, ))
6022 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6028 0, 0, 0,
6032 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
6036 0, 0,
6040 0, 0,
6044 0, 0,
6048 0, 0, 0,
6052 0, 0, 0,
6056 0, 0,
6060 0, 0,
6062 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
6063 0, 0, 0, ))
6065 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
6071 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
6073 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
6083 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
6089 0, 0, 0,
6097 0, 0,
6105 0, 0, 0,
6108 0, 0, 0, ))
6110 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
6115 0, 0, 0,
6122 0, 0, 0,
6126 0, 0, 0,
6128 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
6130 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
6133 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
6137 0, 0,
6140 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
6143 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
6146 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
6148 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
6153 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
6155 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
6175 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
6177 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
6181 0, 0, 0,
6185 0, 0, 0,
6188 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6191 0, 0, 0,
6194 FN_I2C1_SDA_D, 0, 0, 0, ))
6196 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6203 0, 0, 0,
6207 0, 0, 0,
6209 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6211 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6213 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6219 0, 0, 0,
6223 0, 0, 0,
6227 0, 0, 0,
6231 0, 0, 0,
6237 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6244 0, 0, 0, 0,
6252 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6258 0, 0,
6262 0, 0,
6278 0, 0, 0,
6286 0, 0, 0, ))
6288 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6294 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
6297 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
6299 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6300 0, 0, 0,
6302 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6303 0, 0, 0,
6305 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6307 0, 0,
6309 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6311 0, 0,
6314 0, 0, 0,
6317 0, 0, 0,
6331 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
6333 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6338 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6340 0, 0,
6342 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6344 0, 0,
6346 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6347 FN_TCLK2, FN_VI1_DATA3_C, 0,
6349 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6350 0, 0, 0,
6352 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6354 0, 0,
6358 0, 0,
6362 0, 0,
6366 0, 0, 0,
6368 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6370 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6372 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
6374 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6387 0, 0, 0,
6391 0, 0, 0, ))
6393 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6408 0, 0, 0, 0,
6410 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6422 0, 0, 0,
6425 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6434 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
6436 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6443 0, 0, 0,
6450 0, 0,
6457 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6464 0, 0, 0,
6466 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6471 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6473 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6480 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6491 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
6493 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6495 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
6501 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6512 0, 0, 0,
6514 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
6517 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6524 0, 0, 0,
6526 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6528 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6539 0, 0, 0,
6545 0, 0, 0,
6552 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6560 if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) in r8a7791_pin_to_pocctrl()
6563 *pocctrl = 0xe606008c; in r8a7791_pin_to_pocctrl()
6565 return 31 - (pin & 0x1f); in r8a7791_pin_to_pocctrl()
6569 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
6570 [ 0] = RCAR_GP_PIN(1, 4), /* A20 */
6576 [ 6] = RCAR_GP_PIN(0, 0), /* D0 */
6577 [ 7] = RCAR_GP_PIN(0, 1), /* D1 */
6578 [ 8] = RCAR_GP_PIN(0, 2), /* D2 */
6579 [ 9] = RCAR_GP_PIN(0, 3), /* D3 */
6580 [10] = RCAR_GP_PIN(0, 4), /* D4 */
6581 [11] = RCAR_GP_PIN(0, 5), /* D5 */
6582 [12] = RCAR_GP_PIN(0, 6), /* D6 */
6583 [13] = RCAR_GP_PIN(0, 7), /* D7 */
6584 [14] = RCAR_GP_PIN(0, 8), /* D8 */
6585 [15] = RCAR_GP_PIN(0, 9), /* D9 */
6586 [16] = RCAR_GP_PIN(0, 10), /* D10 */
6587 [17] = RCAR_GP_PIN(0, 11), /* D11 */
6588 [18] = RCAR_GP_PIN(0, 12), /* D12 */
6589 [19] = RCAR_GP_PIN(0, 13), /* D13 */
6590 [20] = RCAR_GP_PIN(0, 14), /* D14 */
6591 [21] = RCAR_GP_PIN(0, 15), /* D15 */
6592 [22] = RCAR_GP_PIN(0, 16), /* A0 */
6593 [23] = RCAR_GP_PIN(0, 17), /* A1 */
6594 [24] = RCAR_GP_PIN(0, 18), /* A2 */
6595 [25] = RCAR_GP_PIN(0, 19), /* A3 */
6596 [26] = RCAR_GP_PIN(0, 20), /* A4 */
6597 [27] = RCAR_GP_PIN(0, 21), /* A5 */
6598 [28] = RCAR_GP_PIN(0, 22), /* A6 */
6599 [29] = RCAR_GP_PIN(0, 23), /* A7 */
6600 [30] = RCAR_GP_PIN(0, 24), /* A8 */
6601 [31] = RCAR_GP_PIN(0, 25), /* A9 */
6603 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
6604 [ 0] = RCAR_GP_PIN(0, 26), /* A10 */
6605 [ 1] = RCAR_GP_PIN(0, 27), /* A11 */
6606 [ 2] = RCAR_GP_PIN(0, 28), /* A12 */
6607 [ 3] = RCAR_GP_PIN(0, 29), /* A13 */
6608 [ 4] = RCAR_GP_PIN(0, 30), /* A14 */
6609 [ 5] = RCAR_GP_PIN(0, 31), /* A15 */
6610 [ 6] = RCAR_GP_PIN(1, 0), /* A16 */
6634 [30] = RCAR_GP_PIN(2, 0), /* SSI_SCK0129 */
6637 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
6638 [ 0] = RCAR_GP_PIN(2, 2), /* SSI_SDATA0 */
6671 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
6672 [ 0] = RCAR_GP_PIN(7, 12), /* IRQ2 */
6680 [ 8] = RCAR_GP_PIN(3, 0), /* DU1_DR0 */
6705 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
6706 [ 0] = RCAR_GP_PIN(3, 24), /* DU1_DOTCLKIN */
6714 [ 8] = RCAR_GP_PIN(4, 0), /* VI0_CLK */
6739 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
6740 [ 0] = RCAR_GP_PIN(4, 24), /* VI0_R3 */
6745 [ 5] = RCAR_GP_PIN(5, 0), /* VI1_HSYNC# */
6773 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
6774 [ 0] = RCAR_GP_PIN(5, 27), /* STP_ISD_0 */
6778 [ 4] = RCAR_GP_PIN(6, 0), /* SD0_CLK */
6807 { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
6809 [ 0] = RCAR_GP_PIN(6, 28), /* MSIOF0_SS1 */
6817 [ 8] = RCAR_GP_PIN(7, 0), /* HCTS0# */
6842 { PINMUX_BIAS_REG("N/A", 0, "PUPR7", 0xe606011c) {
6844 [ 0] = SH_PFC_PIN_NONE,
6890 .unlock_reg = 0xe6060000, /* PMMR */
6913 .unlock_reg = 0xe6060000, /* PMMR */
6936 .unlock_reg = 0xe6060000, /* PMMR */
6961 .unlock_reg = 0xe6060000, /* PMMR */