Lines Matching +full:0 +full:xe6060000
24 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
43 PINMUX_RESERVED = 0,
1780 RCAR_GP_PIN(0, 23),
1825 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1826 RCAR_GP_PIN(0, 11),
1828 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1847 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1848 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1849 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1851 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1973 /* R[7:0], G[7:0], B[7:0] */
2007 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
2075 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2259 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2266 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2333 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2340 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2400 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2409 /* D[0:7] */
2428 /* D[0:7] */
2577 RCAR_GP_PIN(0, 18),
2584 RCAR_GP_PIN(0, 19),
2598 RCAR_GP_PIN(0, 20),
2606 RCAR_GP_PIN(0, 27),
2613 RCAR_GP_PIN(0, 26),
2620 RCAR_GP_PIN(0, 30),
2627 RCAR_GP_PIN(0, 31),
2634 RCAR_GP_PIN(0, 29),
2641 RCAR_GP_PIN(0, 28),
2692 RCAR_GP_PIN(0, 0),
2699 RCAR_GP_PIN(0, 1),
2706 RCAR_GP_PIN(0, 2),
2713 RCAR_GP_PIN(0, 3),
2750 RCAR_GP_PIN(0, 16),
2756 RCAR_GP_PIN(0, 17),
2762 RCAR_GP_PIN(0, 18),
2768 RCAR_GP_PIN(0, 19),
2813 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2821 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2842 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2899 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2950 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2971 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2978 RCAR_GP_PIN(0, 23),
2985 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2992 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2999 RCAR_GP_PIN(0, 8),
3006 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
3120 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3170 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3198 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3241 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3248 RCAR_GP_PIN(0, 31),
3255 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3262 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3284 /* D[0:3] */
3292 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3313 /* D[0:3] */
3342 /* D[0:3] */
3371 /* D[0:3] */
3478 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3584 RCAR_GP_PIN(0, 20),
3591 RCAR_GP_PIN(0, 21),
3598 RCAR_GP_PIN(0, 22),
3605 RCAR_GP_PIN(0, 23),
3642 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3643 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3644 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3645 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3647 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3648 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3649 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3650 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3675 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3676 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3677 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3679 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3680 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3681 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3698 RCAR_GP_PIN(0, 12), /* HSYNC */
3699 RCAR_GP_PIN(0, 13), /* VSYNC */
3706 RCAR_GP_PIN(0, 15),
3712 RCAR_GP_PIN(0, 14),
3718 RCAR_GP_PIN(2, 0),
3736 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3737 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3768 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3788 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3798 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3799 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3830 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3903 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3904 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3905 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3906 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3908 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3909 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3937 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3938 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3939 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3941 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3991 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3992 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3993 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3994 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4292 SH_PFC_PIN_GROUP_SUBSET(usb0_ovc_vbus, usb0, 0, 1),
4294 SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1),
4920 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4954 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
4955 0, 0,
4956 0, 0,
4988 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
4989 0, 0,
4990 0, 0,
5022 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
5056 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
5090 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
5124 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5129 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
5131 0, 0, 0, 0, 0, 0, 0, 0, 0,
5135 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
5138 FN_I2C2_SCL_C, 0, 0,
5142 0, 0, 0, 0, 0, 0, 0, 0, 0,
5146 0, 0, 0, 0, 0, 0, 0, 0, 0,
5149 0, 0, 0,
5152 0, 0, 0,
5155 0, 0, 0,
5158 0, 0, 0, ))
5160 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5165 FN_A1, FN_PWM4, 0, 0,
5167 FN_A0, FN_PWM3, 0, 0,
5171 0, 0, 0, 0, 0, 0, 0, 0, 0,
5175 0, 0, 0, 0, 0, 0, 0, 0, 0,
5179 0, 0, 0,
5183 0, 0,
5185 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
5187 0, 0, 0, 0, 0, 0, 0, 0, 0,
5189 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
5191 0, 0, 0, 0, 0, 0, 0, 0, 0,
5193 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
5195 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
5197 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5203 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
5207 0, 0, 0, 0, 0, 0, 0, 0,
5211 0, 0, 0, 0, 0, 0, 0, 0,
5214 0, 0, 0, 0,
5216 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
5218 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
5220 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
5222 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
5224 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, ))
5226 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5231 0, 0, 0,
5234 0, 0, 0, 0,
5236 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
5238 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
5240 FN_A16, FN_ATAWR1_N, 0, 0,
5243 0, 0, 0, 0,
5246 0, 0, 0, 0,
5250 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
5254 0, 0, 0, 0, 0, 0, 0, 0, 0,
5257 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
5258 0, 0, 0, 0, 0, 0, 0, 0, ))
5260 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5266 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
5269 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
5272 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
5275 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
5278 0, 0, 0,
5281 FN_VI2_FIELD_B, 0, 0,
5284 FN_VI2_CLKENB_B, 0, 0,
5286 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
5288 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
5290 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
5293 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5299 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
5301 FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B,
5302 FN_HRX0_B, FN_MSIOF0_SCK_B, 0,
5308 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
5311 0, 0, 0,
5313 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
5316 0, 0,
5320 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
5327 FN_VI2_R3, 0, 0, ))
5329 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5333 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
5334 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
5336 FN_ETH_LINK, 0, FN_HTX0_E,
5337 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
5339 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
5342 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
5343 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
5345 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
5346 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
5348 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
5350 FN_I2C2_SCL_E, 0,
5352 FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B,
5353 FN_MSIOF0_RXD_B, 0, 0,
5357 FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0,
5360 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
5362 FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N,
5363 FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
5365 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5370 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
5372 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
5374 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
5377 0, 0, 0,
5380 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
5383 FN_GLO_SS_C, 0, 0, 0,
5385 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
5386 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
5388 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
5389 FN_GLO_SCLK_C, 0, 0, 0,
5391 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
5393 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
5395 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
5397 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
5398 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
5400 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5406 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
5415 FN_AVB_MAGIC, 0,
5417 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
5419 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
5421 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
5423 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
5425 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
5427 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
5429 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
5431 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
5433 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
5435 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
5437 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5439 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
5441 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5447 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
5449 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
5451 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
5453 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
5455 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
5457 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
5459 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
5463 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
5467 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
5469 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
5471 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
5473 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5475 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
5477 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5484 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
5489 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
5491 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
5493 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
5496 0, 0, 0, 0, 0, 0,
5501 0, 0, 0, 0, 0, 0, 0,
5506 0, 0, 0, 0, 0, 0, 0,
5510 FN_VI3_DATA0_B, 0,
5514 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
5516 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5520 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5522 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
5523 0, 0, 0,
5526 0, 0, 0,
5528 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
5531 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
5534 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5536 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5538 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5540 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5542 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5544 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5550 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
5552 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5559 FN_CAN_DEBUGOUT4, 0, 0,
5563 FN_CAN_DEBUGOUT3, 0, 0,
5569 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5572 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5575 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5578 FN_CAN_STEP0, 0, 0, 0,
5581 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5585 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5587 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5589 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
5591 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5596 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5599 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5602 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5606 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
5609 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5612 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5614 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
5615 FN_CAN_DEBUGOUT8, 0, 0,
5618 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5620 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
5622 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
5625 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
5627 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5634 FN_HRTS0_N_C, 0,
5637 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5640 FN_LCDOUT9, 0, 0, 0,
5643 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5646 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5650 0, 0, 0, 0, 0, 0, 0,
5653 0, 0, 0,
5656 0, 0, 0,
5663 FN_REMOCON, 0, ))
5665 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5675 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
5678 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5684 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5686 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5689 0, 0, 0,
5692 FN_IIC2_SDA, FN_I2C2_SDA, 0,
5695 FN_IIC2_SCL, FN_I2C2_SCL, 0,
5698 FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
5700 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5710 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
5713 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
5715 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5721 FN_SEL_SCIF1_4, 0, 0, 0,
5723 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5725 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5729 FN_SEL_SCIFB1_6, 0,
5740 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5744 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5754 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5765 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5781 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5793 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5796 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5798 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
5801 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5803 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
5805 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5814 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5818 FN_SEL_IIC2_4, 0, 0, 0,
5820 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5823 FN_SEL_I2C2_4, 0, 0, 0,
5825 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
5832 if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31)) in r8a7790_pin_to_pocctrl()
5835 *pocctrl = 0xe606008c; in r8a7790_pin_to_pocctrl()
5837 return 31 - (pin & 0x1f); in r8a7790_pin_to_pocctrl()
5841 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
5842 [ 0] = RCAR_GP_PIN(0, 16), /* A0 */
5843 [ 1] = RCAR_GP_PIN(0, 17), /* A1 */
5844 [ 2] = RCAR_GP_PIN(0, 18), /* A2 */
5845 [ 3] = RCAR_GP_PIN(0, 19), /* A3 */
5846 [ 4] = RCAR_GP_PIN(0, 20), /* A4 */
5847 [ 5] = RCAR_GP_PIN(0, 21), /* A5 */
5848 [ 6] = RCAR_GP_PIN(0, 22), /* A6 */
5849 [ 7] = RCAR_GP_PIN(0, 23), /* A7 */
5850 [ 8] = RCAR_GP_PIN(0, 24), /* A8 */
5851 [ 9] = RCAR_GP_PIN(0, 25), /* A9 */
5852 [10] = RCAR_GP_PIN(0, 26), /* A10 */
5853 [11] = RCAR_GP_PIN(0, 27), /* A11 */
5854 [12] = RCAR_GP_PIN(0, 28), /* A12 */
5855 [13] = RCAR_GP_PIN(0, 29), /* A13 */
5856 [14] = RCAR_GP_PIN(0, 30), /* A14 */
5857 [15] = RCAR_GP_PIN(0, 31), /* A15 */
5858 [16] = RCAR_GP_PIN(1, 0), /* A16 */
5875 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
5877 [ 0] = RCAR_GP_PIN(1, 18), /* BS# */
5893 [16] = RCAR_GP_PIN(0, 0), /* D0 */
5894 [17] = RCAR_GP_PIN(0, 1), /* D1 */
5895 [18] = RCAR_GP_PIN(0, 2), /* D2 */
5896 [19] = RCAR_GP_PIN(0, 3), /* D3 */
5897 [20] = RCAR_GP_PIN(0, 4), /* D4 */
5898 [21] = RCAR_GP_PIN(0, 5), /* D5 */
5899 [22] = RCAR_GP_PIN(0, 6), /* D6 */
5900 [23] = RCAR_GP_PIN(0, 7), /* D7 */
5901 [24] = RCAR_GP_PIN(0, 8), /* D8 */
5902 [25] = RCAR_GP_PIN(0, 9), /* D9 */
5903 [26] = RCAR_GP_PIN(0, 10), /* D10 */
5904 [27] = RCAR_GP_PIN(0, 11), /* D11 */
5905 [28] = RCAR_GP_PIN(0, 12), /* D12 */
5906 [29] = RCAR_GP_PIN(0, 13), /* D13 */
5907 [30] = RCAR_GP_PIN(0, 14), /* D14 */
5908 [31] = RCAR_GP_PIN(0, 15), /* D15 */
5910 { PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) {
5912 [ 0] = SH_PFC_PIN_NONE,
5945 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
5946 [ 0] = RCAR_GP_PIN(5, 28), /* DU_DOTCLKIN2 */
5951 [ 5] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
5973 [27] = RCAR_GP_PIN(4, 0), /* MLB_CLK */
5979 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
5980 [ 0] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6013 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
6014 [ 0] = RCAR_GP_PIN(4, 3), /* SSI_SCK0129 */
6047 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
6048 [ 0] = RCAR_GP_PIN(4, 27), /* SCIFA0_SCK */
6053 [ 5] = RCAR_GP_PIN(5, 0), /* SCIFA1_RXD */
6081 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
6082 [ 0] = RCAR_GP_PIN(2, 23), /* ETH_REF_CLK */
6119 { .soc_id = "r8a7790", .revision = "ES1.0" },
6127 sh_pfc_write(pfc, 0xe6060088, 0x00155554); in r8a7790_pinmux_soc_init()
6129 return 0; in r8a7790_pinmux_soc_init()
6143 .unlock_reg = 0xe6060000, /* PMMR */
6166 .unlock_reg = 0xe6060000, /* PMMR */