Lines Matching refs:pctrl
128 struct pinctrl_dev *pctrl;
167 static int pm8xxx_mpp_update(struct pm8xxx_mpp *pctrl,
236 ret = regmap_write(pctrl->regmap, pin->reg, val);
238 dev_err(pctrl->dev, "failed to write register\n");
245 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
247 return pctrl->npins;
262 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
264 *pins = &pctrl->desc.pins[group].number;
294 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
297 *num_groups = pctrl->npins;
305 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
306 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
309 pm8xxx_mpp_update(pctrl, pin);
325 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
326 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
375 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
376 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
418 dev_err(pctrl->dev,
425 pm8xxx_mpp_update(pctrl, pin);
447 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip);
448 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
462 pm8xxx_mpp_update(pctrl, pin);
471 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip);
472 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
488 pm8xxx_mpp_update(pctrl, pin);
495 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip);
496 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
516 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip);
517 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
521 pm8xxx_mpp_update(pctrl, pin);
546 struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip);
547 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
642 static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl,
651 ret = regmap_read(pctrl->regmap, pin->reg, &val);
653 dev_err(pctrl->dev, "failed to read register\n");
734 struct pm8xxx_mpp *pctrl = container_of(domain->host_data,
739 fwspec->param[0] > pctrl->chip.ngpio)
822 struct pm8xxx_mpp *pctrl;
826 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
827 if (!pctrl)
830 pctrl->dev = &pdev->dev;
831 pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev);
833 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
834 if (!pctrl->regmap) {
839 pctrl->desc = pm8xxx_pinctrl_desc;
840 pctrl->desc.npins = pctrl->npins;
843 pctrl->desc.npins,
850 pctrl->desc.npins,
856 for (i = 0; i < pctrl->desc.npins; i++) {
859 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
867 pctrl->desc.pins = pins;
869 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_mpp_bindings);
870 pctrl->desc.custom_params = pm8xxx_mpp_bindings;
872 pctrl->desc.custom_conf_items = pm8xxx_conf_items;
875 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
876 if (IS_ERR(pctrl->pctrl)) {
878 return PTR_ERR(pctrl->pctrl);
881 pctrl->chip = pm8xxx_mpp_template;
882 pctrl->chip.base = -1;
883 pctrl->chip.parent = &pdev->dev;
884 pctrl->chip.of_gpio_n_cells = 2;
885 pctrl->chip.label = dev_name(pctrl->dev);
886 pctrl->chip.ngpio = pctrl->npins;
888 parent_node = of_irq_find_parent(pctrl->dev->of_node);
897 girq = &pctrl->chip.irq;
901 girq->fwnode = dev_fwnode(pctrl->dev);
911 ret = gpiochip_add_data(&pctrl->chip, pctrl);
917 ret = gpiochip_add_pin_range(&pctrl->chip,
918 dev_name(pctrl->dev),
919 0, 0, pctrl->chip.ngpio);
921 dev_err(pctrl->dev, "failed to add pin range\n");
925 platform_set_drvdata(pdev, pctrl);
932 gpiochip_remove(&pctrl->chip);
939 struct pm8xxx_mpp *pctrl = platform_get_drvdata(pdev);
941 gpiochip_remove(&pctrl->chip);