Lines Matching +full:0 +full:x8f000
12 #define REG_SIZE 0x1000
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
38 .pull_bit = 0, \
43 .in_bit = 0, \
45 .intr_enable_bit = 0, \
46 .intr_status_bit = 0, \
61 .io_reg = 0, \
62 .intr_cfg_reg = 0, \
63 .intr_status_reg = 0, \
64 .intr_target_reg = 0, \
86 .io_reg = offset + 0x4, \
87 .intr_cfg_reg = 0, \
88 .intr_status_reg = 0, \
89 .intr_target_reg = 0, \
92 .drv_bit = 0, \
95 .out_bit = 0, \
113 PINCTRL_PIN(0, "GPIO_0"),
261 DECLARE_MSM_GPIO_PINS(0);
804 [0] = PINGROUP(0, qup1_se0, ibi_i3c_qup1, cmu_rng, qdss_gpio, _, _, _, _, _),
940 [136] = UFS_RESET(ufs_reset, 0x97000),
941 [137] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x8c004, 0, 0),
942 [138] = SDC_QDSD_PINGROUP(sdc1_clk, 0x8c000, 13, 6),
943 [139] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x8c000, 11, 3),
944 [140] = SDC_QDSD_PINGROUP(sdc1_data, 0x8c000, 9, 0),
945 [141] = SDC_QDSD_PINGROUP(sdc2_clk, 0x8f000, 14, 6),
946 [142] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x8f000, 11, 3),
947 [143] = SDC_QDSD_PINGROUP(sdc2_data, 0x8f000, 9, 0),
951 { 0, 67 }, { 3, 82 }, { 4, 69 }, { 5, 70 }, { 6, 44 }, { 7, 43 },