Lines Matching +full:wakeup +full:- +full:interrupt +full:- +full:controller

1 /* SPDX-License-Identifier: GPL-2.0-only */
38  * struct msm_pingroup - Qualcomm pingroup definition
47  * @intr_cfg_reg:         Offset of the register holding interrupt configuration bits.
58  * @intr_enable_bit:      Offset in @intr_cfg_reg for enabling the interrupt for this group.
59  * @intr_status_bit:      Offset in @intr_status_reg for reading and acking the interrupt
62  *			  wakeup events.
63  * @intr_wakeup_enable_bit: Offset in @intr_target_reg to enable wakeup events for the GPIO.
64  * @intr_target_bit:      Offset in @intr_target_reg for configuring the interrupt routing.
65  * @intr_target_width:    Number of bits used for specifying interrupt routing target.
66  * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
69  * @intr_polarity_bit:    Offset in @intr_cfg_reg for specifying polarity of the interrupt.
70  * @intr_detection_bit:   Offset in @intr_cfg_reg for specifying interrupt type.
71  * @intr_detection_width: Number of bits used for specifying interrupt type,
118  * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
119  * @gpio:          The GPIOs that are wakeup capable
120  * @wakeirq:       The interrupt at the always-on interrupt controller
128  * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
129  * @pins:	    An array describing all pins the pin controller affects.
137  * @wakeirq_map:    The map of wakeup capable GPIOs and the pin at PDC/MPM
143  * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in
144  *              hardware this is a mux 1-level above the TLMM, we'll treat