Lines Matching refs:pctrl
63 struct pinctrl_dev *pctrl; member
85 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
88 return readl(pctrl->regs[g->tile] + g->name##_reg); \
90 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
93 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
102 static void msm_ack_intr_status(struct msm_pinctrl *pctrl, in MSM_ACCESSOR()
107 msm_writel_intr_status(val, pctrl, g); in MSM_ACCESSOR()
112 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_groups_count() local
114 return pctrl->soc->ngroups; in msm_get_groups_count()
120 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_name() local
122 return pctrl->soc->groups[group].grp.name; in msm_get_group_name()
130 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_pins() local
132 *pins = pctrl->soc->groups[group].grp.pins; in msm_get_group_pins()
133 *num_pins = pctrl->soc->groups[group].grp.npins; in msm_get_group_pins()
147 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request() local
148 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
155 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_functions_count() local
157 return pctrl->soc->nfunctions; in msm_get_functions_count()
163 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_name() local
165 return pctrl->soc->functions[function].name; in msm_get_function_name()
173 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_groups() local
175 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
176 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
184 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_set_mux() local
185 struct gpio_chip *gc = &pctrl->chip; in msm_pinmux_set_mux()
188 unsigned int gpio_func = pctrl->soc->gpio_func; in msm_pinmux_set_mux()
189 unsigned int egpio_func = pctrl->soc->egpio_func; in msm_pinmux_set_mux()
195 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
217 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) in msm_pinmux_set_mux()
220 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
222 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
231 !test_and_set_bit(group, pctrl->ever_gpio)) { in msm_pinmux_set_mux()
232 u32 io_val = msm_readl_io(pctrl, g); in msm_pinmux_set_mux()
236 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
239 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
254 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
256 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
259 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { in msm_pinmux_set_mux()
264 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_pinmux_set_mux()
267 msm_ack_intr_status(pctrl, g); in msm_pinmux_set_mux()
279 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request_gpio() local
280 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
286 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
298 static int msm_config_reg(struct msm_pinctrl *pctrl, in msm_config_reg() argument
352 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_get() local
361 if (!gpiochip_line_is_valid(&pctrl->chip, group)) in msm_config_group_get()
364 g = &pctrl->soc->groups[group]; in msm_config_group_get()
366 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
370 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
386 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
394 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
417 val = msm_readl_io(pctrl, g); in msm_config_group_get()
439 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_set() local
449 g = &pctrl->soc->groups[group]; in msm_config_group_set()
455 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
468 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
474 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
493 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
494 val = msm_readl_io(pctrl, g); in msm_config_group_set()
499 msm_writel_io(val, pctrl, g); in msm_config_group_set()
500 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
537 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
544 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
548 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
549 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
552 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
553 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
568 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_input() local
572 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
574 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
576 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
578 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
580 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
588 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_output() local
592 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
594 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
596 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
601 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
603 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
605 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
607 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
614 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get_direction() local
618 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
620 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
629 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get() local
632 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
634 val = msm_readl_io(pctrl, g); in msm_gpio_get()
641 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_set() local
645 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
647 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
649 val = msm_readl_io(pctrl, g); in msm_gpio_set()
654 msm_writel_io(val, pctrl, g); in msm_gpio_set()
656 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
670 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_dbg_show_one() local
695 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
696 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
697 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
704 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one()
720 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
744 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_init_valid_mask() local
747 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
754 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
764 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
775 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
777 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
821 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, in msm_gpio_update_dual_edge_pos() argument
830 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
832 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
834 msm_writel_intr_cfg(pol, pctrl, g); in msm_gpio_update_dual_edge_pos()
836 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
837 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
841 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
848 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_mask() local
856 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
859 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
861 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
863 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
888 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
890 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
892 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
898 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_unmask() local
906 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_unmask()
909 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
911 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
913 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_unmask()
916 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_unmask()
918 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
920 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
926 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_enable() local
933 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
940 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_disable() local
945 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
963 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_update_dual_edge_parent() local
964 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
970 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
983 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
994 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
1000 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_ack() local
1004 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
1005 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1010 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
1012 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
1014 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_ack()
1016 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1017 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
1019 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
1034 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_needs_dual_edge_parent_workaround() local
1037 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
1038 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
1045 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_init_valid_mask() local
1052 g = &pctrl->soc->groups[i]; in msm_gpio_irq_init_valid_mask()
1063 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_type() local
1070 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1079 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
1080 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1085 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
1087 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1093 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1095 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1104 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
1105 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1114 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
1118 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
1121 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
1129 val = oldval = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
1177 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
1187 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_set_type()
1189 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1190 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
1192 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1205 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_wake() local
1213 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1216 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1222 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_reqres() local
1223 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_reqres()
1230 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1258 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { in msm_gpio_irq_reqres()
1261 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_reqres()
1263 intr_cfg = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_reqres()
1266 msm_writel_intr_cfg(intr_cfg, pctrl, g); in msm_gpio_irq_reqres()
1269 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_reqres()
1281 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_relres() local
1282 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_relres()
1286 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { in msm_gpio_irq_relres()
1289 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_relres()
1291 intr_cfg = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_relres()
1294 msm_writel_intr_cfg(intr_cfg, pctrl, g); in msm_gpio_irq_relres()
1297 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_relres()
1308 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_affinity() local
1310 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1319 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_vcpu_affinity() local
1321 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1331 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_handler() local
1343 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1344 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1345 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
1365 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_wakeirq() local
1372 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1373 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1383 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) in msm_gpio_needs_valid_mask() argument
1385 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1388 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1411 static int msm_gpio_init(struct msm_pinctrl *pctrl) in msm_gpio_init() argument
1416 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1423 chip = &pctrl->chip; in msm_gpio_init()
1426 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1427 chip->parent = pctrl->dev; in msm_gpio_init()
1429 if (msm_gpio_needs_valid_mask(pctrl)) in msm_gpio_init()
1432 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1445 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1446 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1447 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1454 girq->fwnode = dev_fwnode(pctrl->dev); in msm_gpio_init()
1456 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1462 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1465 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); in msm_gpio_init()
1467 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1481 if (!of_property_present(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1482 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1483 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1485 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1495 struct msm_pinctrl *pctrl = data->cb_data; in msm_ps_hold_restart() local
1497 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1513 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) in msm_pinctrl_setup_pm_reset() argument
1516 const struct pinfunction *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1518 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1520 if (devm_register_sys_off_handler(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1524 pctrl)) in msm_pinctrl_setup_pm_reset()
1525 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1527 poweroff_pctrl = pctrl; in msm_pinctrl_setup_pm_reset()
1535 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_suspend() local
1537 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1542 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_resume() local
1544 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1555 struct msm_pinctrl *pctrl; in msm_pinctrl_probe() local
1560 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1561 if (!pctrl) in msm_pinctrl_probe()
1564 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1565 pctrl->soc = soc_data; in msm_pinctrl_probe()
1566 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1567 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1568 pctrl->dev->of_node, in msm_pinctrl_probe()
1571 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1577 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1578 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1579 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1582 pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in msm_pinctrl_probe()
1583 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1584 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1586 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1589 msm_pinctrl_setup_pm_reset(pctrl); in msm_pinctrl_probe()
1591 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1592 if (pctrl->irq < 0) in msm_pinctrl_probe()
1593 return pctrl->irq; in msm_pinctrl_probe()
1595 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1596 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1597 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1598 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1599 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1600 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1601 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1603 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1604 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1606 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1609 ret = msm_gpio_init(pctrl); in msm_pinctrl_probe()
1613 platform_set_drvdata(pdev, pctrl); in msm_pinctrl_probe()