87 			    const struct msm_pingroup *g) \
89 	return readl(pctrl->regs[g->tile] + g->name##_reg); \
92 			      const struct msm_pingroup *g) \
94 	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
104 				const struct msm_pingroup *g)  in MSM_ACCESSOR()
106 	u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;  in MSM_ACCESSOR()
108 	msm_writel_intr_status(val, pctrl, g);  in MSM_ACCESSOR()
191 	const struct msm_pingroup *g;  in msm_pinmux_set_mux()  local
196 	g = &pctrl->soc->groups[group];  in msm_pinmux_set_mux()
197 	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);  in msm_pinmux_set_mux()
199 	for (i = 0; i < g->nfuncs; i++) {  in msm_pinmux_set_mux()
200 		if (g->funcs[i] == function)  in msm_pinmux_set_mux()
204 	if (WARN_ON(i == g->nfuncs))  in msm_pinmux_set_mux()
223 	val = msm_readl_ctl(pctrl, g);  in msm_pinmux_set_mux()
231 	if (i == gpio_func && (val & BIT(g->oe_bit)) &&  in msm_pinmux_set_mux()
233 		u32 io_val = msm_readl_io(pctrl, g);  in msm_pinmux_set_mux()
235 		if (io_val & BIT(g->in_bit)) {  in msm_pinmux_set_mux()
236 			if (!(io_val & BIT(g->out_bit)))  in msm_pinmux_set_mux()
237 				msm_writel_io(io_val | BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
239 			if (io_val & BIT(g->out_bit))  in msm_pinmux_set_mux()
240 				msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g);  in msm_pinmux_set_mux()
245 		if (val & BIT(g->egpio_present))  in msm_pinmux_set_mux()
246 			val &= ~BIT(g->egpio_enable);  in msm_pinmux_set_mux()
249 		val |= i << g->mux_bit;  in msm_pinmux_set_mux()
251 		if (egpio_func && val & BIT(g->egpio_present))  in msm_pinmux_set_mux()
252 			val |= BIT(g->egpio_enable);  in msm_pinmux_set_mux()
255 	msm_writel_ctl(val, pctrl, g);  in msm_pinmux_set_mux()
268 			msm_ack_intr_status(pctrl, g);  in msm_pinmux_set_mux()
281 	const struct msm_pingroup *g = &pctrl->soc->groups[offset];  in msm_pinmux_request_gpio()  local
284 	if (!g->nfuncs)  in msm_pinmux_request_gpio()
287 	return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);  in msm_pinmux_request_gpio()
300 			  const struct msm_pingroup *g,  in msm_config_reg()  argument
310 		*bit = g->pull_bit;  in msm_config_reg()
312 		if (g->i2c_pull_bit)  in msm_config_reg()
313 			*mask |= BIT(g->i2c_pull_bit) >> *bit;  in msm_config_reg()
316 		*bit = g->od_bit;  in msm_config_reg()
320 		*bit = g->drv_bit;  in msm_config_reg()
326 		*bit = g->oe_bit;  in msm_config_reg()
352 	const struct msm_pingroup *g;  in msm_config_group_get()  local
365 	g = &pctrl->soc->groups[group];  in msm_config_group_get()
367 	ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_get()
371 	val = msm_readl_ctl(pctrl, g);  in msm_config_group_get()
397 		else if (arg & BIT(g->i2c_pull_bit))  in msm_config_group_get()
418 		val = msm_readl_io(pctrl, g);  in msm_config_group_get()
419 		arg = !!(val & BIT(g->in_bit));  in msm_config_group_get()
439 	const struct msm_pingroup *g;  in msm_config_group_set()  local
450 	g = &pctrl->soc->groups[group];  in msm_config_group_set()
456 		ret = msm_config_reg(pctrl, g, param, &mask, &bit);  in msm_config_group_set()
477 			else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP)  in msm_config_group_set()
478 				arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP;  in msm_config_group_set()
495 			val = msm_readl_io(pctrl, g);  in msm_config_group_set()
497 				val |= BIT(g->out_bit);  in msm_config_group_set()
499 				val &= ~BIT(g->out_bit);  in msm_config_group_set()
500 			msm_writel_io(val, pctrl, g);  in msm_config_group_set()
550 		val = msm_readl_ctl(pctrl, g);  in msm_config_group_set()
553 		msm_writel_ctl(val, pctrl, g);  in msm_config_group_set()
568 	const struct msm_pingroup *g;  in msm_gpio_direction_input()  local
573 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_input()
577 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_input()
578 	val &= ~BIT(g->oe_bit);  in msm_gpio_direction_input()
579 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_input()
588 	const struct msm_pingroup *g;  in msm_gpio_direction_output()  local
593 	g = &pctrl->soc->groups[offset];  in msm_gpio_direction_output()
597 	val = msm_readl_io(pctrl, g);  in msm_gpio_direction_output()
599 		val |= BIT(g->out_bit);  in msm_gpio_direction_output()
601 		val &= ~BIT(g->out_bit);  in msm_gpio_direction_output()
602 	msm_writel_io(val, pctrl, g);  in msm_gpio_direction_output()
604 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_direction_output()
605 	val |= BIT(g->oe_bit);  in msm_gpio_direction_output()
606 	msm_writel_ctl(val, pctrl, g);  in msm_gpio_direction_output()
616 	const struct msm_pingroup *g;  in msm_gpio_get_direction()  local
619 	g = &pctrl->soc->groups[offset];  in msm_gpio_get_direction()
621 	val = msm_readl_ctl(pctrl, g);  in msm_gpio_get_direction()
623 	return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :  in msm_gpio_get_direction()
629 	const struct msm_pingroup *g;  in msm_gpio_get()  local
633 	g = &pctrl->soc->groups[offset];  in msm_gpio_get()
635 	val = msm_readl_io(pctrl, g);  in msm_gpio_get()
636 	return !!(val & BIT(g->in_bit));  in msm_gpio_get()
641 	const struct msm_pingroup *g;  in msm_gpio_set()  local
646 	g = &pctrl->soc->groups[offset];  in msm_gpio_set()
650 	val = msm_readl_io(pctrl, g);  in msm_gpio_set()
652 		val |= BIT(g->out_bit);  in msm_gpio_set()
654 		val &= ~BIT(g->out_bit);  in msm_gpio_set()
655 	msm_writel_io(val, pctrl, g);  in msm_gpio_set()
668 	const struct msm_pingroup *g;  in msm_gpio_dbg_show_one()  local
694 	g = &pctrl->soc->groups[offset];  in msm_gpio_dbg_show_one()
695 	ctl_reg = msm_readl_ctl(pctrl, g);  in msm_gpio_dbg_show_one()
696 	io_reg = msm_readl_io(pctrl, g);  in msm_gpio_dbg_show_one()
698 	is_out = !!(ctl_reg & BIT(g->oe_bit));  in msm_gpio_dbg_show_one()
699 	func = (ctl_reg >> g->mux_bit) & 7;  in msm_gpio_dbg_show_one()
700 	drive = (ctl_reg >> g->drv_bit) & 7;  in msm_gpio_dbg_show_one()
701 	pull = (ctl_reg >> g->pull_bit) & 3;  in msm_gpio_dbg_show_one()
703 	if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))  in msm_gpio_dbg_show_one()
704 		egpio_enable = !(ctl_reg & BIT(g->egpio_enable));  in msm_gpio_dbg_show_one()
707 		val = !!(io_reg & BIT(g->out_bit));  in msm_gpio_dbg_show_one()
709 		val = !!(io_reg & BIT(g->in_bit));  in msm_gpio_dbg_show_one()
712 		seq_printf(s, " %-8s: egpio\n", g->grp.name);  in msm_gpio_dbg_show_one()
716 	seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in");  in msm_gpio_dbg_show_one()
821 					  const struct msm_pingroup *g,  in msm_gpio_update_dual_edge_pos()  argument
829 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
831 		pol = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_update_dual_edge_pos()
832 		pol ^= BIT(g->intr_polarity_bit);  in msm_gpio_update_dual_edge_pos()
833 		msm_writel_intr_cfg(pol, pctrl, g);  in msm_gpio_update_dual_edge_pos()
835 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_pos()
836 		intstat = msm_readl_intr_status(pctrl, g);  in msm_gpio_update_dual_edge_pos()
848 	const struct msm_pingroup *g;  in msm_gpio_irq_mask()  local
858 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_mask()
862 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_mask()
884 		val &= ~BIT(g->intr_raw_status_bit);  in msm_gpio_irq_mask()
886 	val &= ~BIT(g->intr_enable_bit);  in msm_gpio_irq_mask()
887 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_mask()
898 	const struct msm_pingroup *g;  in msm_gpio_irq_unmask()  local
908 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_unmask()
912 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_unmask()
913 	val |= BIT(g->intr_raw_status_bit);  in msm_gpio_irq_unmask()
914 	val |= BIT(g->intr_enable_bit);  in msm_gpio_irq_unmask()
915 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_unmask()
963 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_update_dual_edge_parent()  local
969 	val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
982 		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);  in msm_gpio_update_dual_edge_parent()
1000 	const struct msm_pingroup *g;  in msm_gpio_irq_ack()  local
1009 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_ack()
1013 	msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_ack()
1016 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_ack()
1044 	const struct msm_pingroup *g;  in msm_gpio_irq_set_type()  local
1066 	g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_set_type()
1073 	if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)  in msm_gpio_irq_set_type()
1082 	if (g->intr_target_width)  in msm_gpio_irq_set_type()
1083 		intr_target_mask = GENMASK(g->intr_target_width - 1, 0);  in msm_gpio_irq_set_type()
1086 		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;  in msm_gpio_irq_set_type()
1090 		val &= ~(intr_target_mask << g->intr_target_bit);  in msm_gpio_irq_set_type()
1091 		val |= g->intr_target_kpss_val << g->intr_target_bit;  in msm_gpio_irq_set_type()
1099 		val = msm_readl_intr_target(pctrl, g);  in msm_gpio_irq_set_type()
1100 		val &= ~(intr_target_mask << g->intr_target_bit);  in msm_gpio_irq_set_type()
1101 		val |= g->intr_target_kpss_val << g->intr_target_bit;  in msm_gpio_irq_set_type()
1102 		msm_writel_intr_target(val, pctrl, g);  in msm_gpio_irq_set_type()
1110 	val = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_set_type()
1111 	was_enabled = val & BIT(g->intr_raw_status_bit);  in msm_gpio_irq_set_type()
1112 	val |= BIT(g->intr_raw_status_bit);  in msm_gpio_irq_set_type()
1113 	if (g->intr_detection_width == 2) {  in msm_gpio_irq_set_type()
1114 		val &= ~(3 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
1115 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1118 			val |= 1 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1119 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1122 			val |= 2 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1123 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1126 			val |= 3 << g->intr_detection_bit;  in msm_gpio_irq_set_type()
1127 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1132 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1135 	} else if (g->intr_detection_width == 1) {  in msm_gpio_irq_set_type()
1136 		val &= ~(1 << g->intr_detection_bit);  in msm_gpio_irq_set_type()
1137 		val &= ~(1 << g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1140 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1141 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1144 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1147 			val |= BIT(g->intr_detection_bit);  in msm_gpio_irq_set_type()
1148 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1153 			val |= BIT(g->intr_polarity_bit);  in msm_gpio_irq_set_type()
1159 	msm_writel_intr_cfg(val, pctrl, g);  in msm_gpio_irq_set_type()
1167 		msm_ack_intr_status(pctrl, g);  in msm_gpio_irq_set_type()
1170 		msm_gpio_update_dual_edge_pos(pctrl, g, d);  in msm_gpio_irq_set_type()
1203 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_reqres()  local
1238 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {  in msm_gpio_irq_reqres()
1243 		intr_cfg = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_reqres()
1244 		if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {  in msm_gpio_irq_reqres()
1245 			intr_cfg |= BIT(g->intr_wakeup_enable_bit);  in msm_gpio_irq_reqres()
1246 			msm_writel_intr_cfg(intr_cfg, pctrl, g);  in msm_gpio_irq_reqres()
1262 	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];  in msm_gpio_irq_relres()  local
1266 	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {  in msm_gpio_irq_relres()
1271 		intr_cfg = msm_readl_intr_cfg(pctrl, g);  in msm_gpio_irq_relres()
1272 		if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {  in msm_gpio_irq_relres()
1273 			intr_cfg &= ~BIT(g->intr_wakeup_enable_bit);  in msm_gpio_irq_relres()
1274 			msm_writel_intr_cfg(intr_cfg, pctrl, g);  in msm_gpio_irq_relres()
1310 	const struct msm_pingroup *g;  in msm_gpio_irq_handler()  local
1324 		g = &pctrl->soc->groups[i];  in msm_gpio_irq_handler()
1325 		val = msm_readl_intr_status(pctrl, g);  in msm_gpio_irq_handler()
1326 		if (val & BIT(g->intr_status_bit)) {  in msm_gpio_irq_handler()